HDL Bits Testbenches

Tb/clock

module top_module ( );
	reg clock;
    
    dut d(clock);
    
    initial 
        clock=0;
    always
        #5ps clock=~clock;
endmodule

Tb/tb1

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
		A=0; B=0;
        #10 A=1; B=0;
        #5  A=1; B=1;
        #5  A=0; B=1;
        #20 A=0; B=0;
    end

endmodule

Tb/and

module top_module();
    reg [1:2] in;
    wire out;
    
    andgate a(in,out);
    initial begin
       	in=2'b00;
        #10 in=2'b01;
        #10 in=2'b10;
        #10 in=2'b11;
    end
endmodule

Tb/tb2

module top_module();
	reg clk,in;
    reg [2:0] s;
    wire out;
    q7 q(clk,in,s,out);
    initial
        clk=0;
    always
        #5 clk=~clk;
    initial begin
        in=0;s=3'd2;
        #10 in=0;s=3'd6;
        #10 in=1;s=3'd2;
        #10 in=0;s=3'd7;
        #10 in=1;s=3'd0;
        #30 in=0;s=3'd0;
    end
        
endmodule

Tb/tff

module top_module ();
	reg clk,reset,t;
    wire q;
    
    tff tf(clk,reset,t,q);
    
    initial
        clk=0;
    always
        #5 clk=~clk;
    initial begin
        reset=0; t=0;
    	#10 reset=1;
    	#20 reset=0;
    	#10 t=1;
    	#10 t=0;
    end
endmodule