Fsm ps2data

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
	
    // FSM from fsm_ps2
    parameter S0=0,S1=1,S2=2,S3=3;
    reg [1:0] state,next_state;
    reg [7:0] temp;
    // State transition logic (combinational)
    always@(*) begin
        case(state) 
            S0: next_state = (in[3])?S1:S0;
            S1: next_state = S2;
            S2: next_state = S3;
            S3: next_state = (in[3])?S1:S0;
            default: next_state = S0;
        endcase
    end
    // State flip-flops (sequential)
    always@(posedge clk) begin
        if(reset)
            state<=S0;
        else
            state<=next_state;
    end
    // Output logic
    assign done=(state==S3);

    // New: Datapath to store incoming bytes.
    always@(*) begin
        case(state)
            S0: temp=(in[3])?in:0;
            S1: out_bytes[23:8]={temp,in};
            S2: out_bytes[7:0]=in;
            S3: temp=(in[3])?in:0;
        endcase
    end

endmodule