VL65 状态机与时钟分频

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
	parameter 	IDLE		= 4'b0000,
				S1  		= 4'b0001,
				S10 		= 4'b0010,
				S100		= 4'b0100,
				S1000		= 4'b1000;
	reg	[3:0] state, next_state;

	always@(posedge clk or negedge rst) begin
		if(!rst)
			state <= IDLE;
		else
			state <= next_state;
	end

	always@(*) begin
		case(state)
			IDLE	: next_state = (rst == 1'b1) ? S1 : IDLE;
			S1		: next_state = S10;
			S10		: next_state = S100;
			S100	: next_state = S1000;
			S1000	: next_state = S1;
			default	: next_state = IDLE;
		endcase
	end

	always@(*) begin
		case(state)
			S1		: clk_out = 1'b1;
			default	: clk_out = 1'b0; 
		endcase
	end

//*************code***********//
endmodule