自同步扰码（帧同步）与伪随机扰码

伪随机扰码网上很多，这里就不多说了。

自同步扰码：输入数据进入移位寄存器。

部分代码：

加扰：

module m_gen5 #(parameter WIDTH = 64)
    (clk,rst_n,din,ena,dout);
    input    clk,rst_n;
    input  [WIDTH-1:0]  din;
    input    ena;
    output reg [WIDTH-1:0]  dout;
wire scram_data_p2s;                //串行输出数据
reg [63:0] out_scramble_data_buf;   //输出缓存
 
 
reg[57:0] scram_state;
reg frame_flag0;
always @(posedge clk or negedge rst_n)
if(!rst_n)
frame_flag0 <= 1'b0;
else if(ena)
frame_flag0 <= 1'b1;
else
frame_flag0 <= frame_flag0;
reg [5:0] cnt;
always@(posedge clk or negedge rst_n)                                                                                                                      
  if(rst_n == 1'b0)                                                        
      cnt <= 6'd63;                                                                                                                               
  else if(cnt == 6'd0)  
      cnt <= 6'd63; 
  else if(ena)
      cnt <= cnt - 6'd1; 
  else 
      cnt <= 6'd63; 
assign scram_data_p2s = din[cnt];     
 if(rst_n == 1'b0)  
  begin                                                      
      out_scramble_data_buf <= 64'b0;  
      scram_state <= {WIDTH{1'b1}}; 
  end 
  else if(ena)
  begin
      out_scramble_data_buf[cnt]<=scram_data_p2s^scram_state[39]^scram_state[0];   
      scram_state <= {scram_data_p2s^scram_state[39]^scram_state[0],scram_state[57:1]};  
  end
  else
  begin
      out_scramble_data_buf <= 64'b0;  
      scram_state <= {WIDTH{1'b1}};   
    end
             
always@(posedge clk or negedge rst_n) 
begin
  if(rst_n == 1'b0) begin
      dout <= {WIDTH{1'b0}};
  end
  else if(cnt == 6'd63)
  begin
      dout   <= out_scramble_data_buf;
  end 
  else  
  begin                      
      dout <= dout;
  end
end 
endmodule

解扰：

module dis_m_gen5 #(parameter WIDTH = 64)
    (clk,rst_n,din,ena,dout);
    input    clk,rst_n;
    input  [WIDTH-1:0]  din;
    input    ena;
    output reg [WIDTH-1:0]  dout;
 wire scram_data_p2s;                //串行输出数据
reg [63:0] out_scramble_data_buf;   //输出缓存
reg[57:0] scram_state;
reg [5:0] cnt;
always@(posedge clk or negedge rst_n)                                                                                                                      
  if(rst_n == 1'b0)                                                        
      cnt <= 6'd63;                                                                                                                               
  else if(cnt == 6'd0)  
      cnt <= 6'd63; 
  else if(ena)
      cnt <= cnt - 6'b1; 
  else 
      cnt <= 6'd63; 
                                                                  
assign scram_data_p2s = din[cnt];
                            
always@(posedge clk or negedge rst_n)                                                                                                                      
  if(rst_n == 1'b0)  
  begin                                                      
      out_scramble_data_buf <= 64'b0;  
      scram_state <= {WIDTH{1'b1}}; 
  end                                                                                                                            
  else if(ena)
  begin
      out_scramble_data_buf[cnt]<=scram_data_p2s^scram_state[39]^scram_state[0];   
      scram_state <= {scram_data_p2s,scram_state[57:1]}; 
  end 
  else
  begin
      out_scramble_data_buf <= 64'b0;  
      scram_state <= {WIDTH{1'b1}}; 
    end
     
always@(posedge clk or negedge rst_n) 
begin
   if(rst_n == 1'b0) begin
      dout <= {WIDTH{1'b0}};
   end
    else if(cnt == 6'd63)
    begin
      dout <= out_scramble_data_buf;
    end 
    else 
    begin                                              
      dout <= dout;                                         
    end                                                
end  
endmodule

自同步扰码仿真结果：

与matlab对比：

matlab部分代码：

%原始数据
din=88;%88   72356734213991099
L=10;
S=58;
WIDTH=64;
%输出
dout_scrambler = zeros(1,L);
dout_descrambler  = zeros(1,L);
scrambler =ones(1,S);    %加扰器移位寄存器初始状态
descrambler = scrambler;      %解扰器移位寄存器初始状态
for k = 1:1:L    
    f =  zeros(1,WIDTH);
    x=dec2bin(din,WIDTH);
    %char转换为数组
    for t = 1:WIDTH
        dd = x(t);
        c = isstrprop(dd,'digit')|isstrprop(dd,'punct');
        cc = dd(c);
        f(t)=str2double(cc);
    end
    y_scrambler = zeros(1,WIDTH);
    
    %画图
    subplot(3,1,1)
    stairs(f)
    axis([0 WIDTH -0.2 1.2])
    title('原始数据');
    
    %--------------加扰器-----------------%
    for i = 1:WIDTH
        z = bitxor(scrambler(58),scrambler(19));  %异或
        y_scrambler(i) = bitxor(z,f(i));
        scrambler=[y_scrambler(i),scrambler(1:S-1)];
    end
    %数组转换为字符串
    dir=0;
    dout_a = ((bit2dec(y_scrambler,dir,WIDTH)));
    dout_scrambler(k) = dout_a;
    
    %画图
    subplot(3,1,2)
    stairs(y_scrambler)
    axis([0 WIDTH -0.2 1.2])
    title('加扰后的数据');

matlab结果

可以看出matlab扰码与verilog扰码输出结果一样。