按照Verilog源程序写法如下:
module shift;
reg [3:0]start,result;
initial;
begin;
start = 1;
result = (start<<2);
end
endmodule
Transcript 命令行中用vlog 指令进行编译,
显示如下错误
参考文章:
verilog error:syntax error-Is there a missing '::'? - nuomiphp
修改代码,加入关键词assgin
module shift;
reg [3:0]start,result;
initial;
begin;
assign start = 1;
assign