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RSS订阅原创 HDLBits刷题_Lemmings4
See also:Lemmings1,Lemmings2, andLemmings3.Although Lemmings can walk, fall, and dig, Lemmings aren't invulnerable. If a Lemming falls for too long then hits the ground, it can splatter. In particular, if a Lemming falls for more than 20 clock cycles ...
2022-01-10 22:32:46
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原创 HDLBits刷题_Lemmings3
See also:Lemmings1andLemmings2.In addition to walking and falling, Lemmings can sometimes be told to do useful things, like dig (it starts digging whendig=1). A Lemming can dig if it is currently walking on ground (ground=1and not falling), and will...
2022-01-10 19:33:18
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原创 HDLBits刷题_Lemmings2
See also:Lemmings1.In addition to walking left and right, Lemmings will fall (and presumably go "aaah!") if the ground disappears underneath them.In addition to walking left and right and changing direction when bumped, whenground=0, the Lemming will..
2022-01-10 19:08:38
325
原创 HDLBits刷题_Exams/ece241 2013 q4 (非状态转移解法)
Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).module top_module ( input clk, input reset,
2022-01-10 16:50:19
437
原创 HDLBits刷题_Fsm1s
This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.This exercise is the same asfsm1, but using synchronous reset.解题思路：原代码中else的end位置给错，需要注意// Note the Verilog-..
2022-01-07 20:59:12
757
原创 HDLBits刷题_Count clock
Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).reset resets the clock to 12:00 AM. pm
2022-01-03 16:43:30
535
原创 HDLBits刷题_Edgecapture
For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (synchronous reset).Each output bit behaves like a SR flip-flop: The
2022-01-01 21:54:34
449
原创 HDLBits刷题_Verilog Language_Bcdadd100
You are provided with a BCD one-digit adder namedbcd_faddthat adds two BCD digits and carry-in, and produces a sum and carry-out.module bcd_fadd { input [3:0] a, input [3:0] b, input cin, output cout, output [3:0] sum );In..
2021-12-23 20:33:15
255
原创 HDLBits刷题_Verilog Language_Popcount255
A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 255-bit input vector.易错要点：不可用 assign out = 8'b0000_0000；因为assign表示out始终接入低电平module top_module( input [254:0] in, output [7:0] ou
2021-12-22 22:48:58
739
原创 HDLBits刷题_Verilog Language_Vector100r
Given a 100-bit input vector [99:0], reverse its bit ordering.module top_module( input [99:0] in, output [99:0] out); always @(*) begin for (int i=0; i < 100; i = i + 1) out[99-i] = in[i]; end endmodule
2021-12-22 22:16:17
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原创 HDLBits刷题_Verilog Language_Gates100
Build a combinational circuit with 100 inputs,in[99:0].There are 3 outputs:out_and: output of a 100-input AND gate. out_or: output of a 100-input OR gate. out_xor: output of a 100-input XOR gate. module top_module( input [99:0] in, output.
2021-12-22 21:48:19
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原创 HDLBits刷题_Verilog Language_Reduction
You're already familiar with bitwise operations between two values, e.g.,a & bora ^ b. Sometimes, you want to create a wide gate that operates on all of the bits ofonevector, like(a[0] & a[1] & a[2] & a[3] ... ), which gets tedious if...
2021-12-22 21:45:03
176
原创 HDLBits刷题_Verilog Language_Conditional
Verilog has a ternary conditional operator (?: ) much like C:(condition? if_true: if_false)This can be used to choose one of two values based oncondition(a mux!) on one line, without using an if-then inside a combinational always block.Examples...
2021-12-22 21:38:25
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原创 HDLBits刷题_Verilog Language_Always nolatches
Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapp
2021-12-22 09:06:07
515
原创 HDLBits刷题_Verilog Language_Always casez
Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8'b10010000 should output 3'd4, because bit[
2021-12-22 09:04:38
175
原创 HDLBits刷题_Verilog Language_Always if
Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8'b10010000 should output 3'd4, because bit[
2021-12-21 21:52:48
219
原创 HDLBits刷题_Verilog Language_Always case2
Apriority encoderis a combinational circuit that, when given an input bit vector, outputs the position of the first1bit in the vector. For example, a 8-bit priority encoder given the input8'b10010000would output3'd4, because bit[4] is first bit that...
2021-12-21 21:05:37
341
原创 HDLBits刷题_Verilog Language_Always case
Case statements in Verilog are nearly equivalent to a sequence of if-elseif-else that compares one expression to a list of others. Its syntax and functionality differs from theswitchstatement in C.always @(*) begin // This is a combinational cir..
2021-12-21 20:48:29
431
原创 HDLBits刷题_Verilog Language_Always if
A common source of errors: How to avoid making latchesWhen designing circuits, youmustthink first in terms of circuits:I want this logic gate I want acombinationalblob of logic that has these inputs and produces these outputs I want a combination...
2021-12-21 19:29:44
437
原创 HDLBits刷题_Verilog Language_Always if
Anifstatement usually creates a 2-to-1 multiplexer, selecting one input if the condition is true, and the other input if the condition is false.always @(*) begin if (condition) begin out = x; end else begin out = y; e..
2021-12-21 18:46:30
441
原创 HDLBits刷题_Verilog Language_Alwaysblock2
For hardware synthesis, there are two types ofalwaysblocks that are relevant:Combinational:always @(*) Clocked:always @(posedge clk)Clocked always blocks create a blob of combinational logic just like combinational always blocks, but also creates a...
2021-12-21 18:39:01
210
原创 HDLBits刷题_Verilog Language_Alwaysblock1
Since digital circuits are composed of logic gates connected with wires, any circuit can be expressed as some combination of modules and assign statements. However, sometimes this is not the most convenient way to describe the circuit.Procedures(of which..
2021-12-21 18:17:20
162
原创 HDLBits刷题_Verilog Language_Module addsub
An adder-subtractor can be built from an adder by optionally negating one of the inputs, which is equivalent to inverting the input then adding 1. The net result is a circuit that can do two operations: (a + b + 0) and (a + ~b + 1). SeeWikipediaif you wa..
2021-12-21 17:07:37
284
原创 HDLBits刷题_Verilog Language_Module cseladd
One drawback of the ripple carry adder (Seeprevious exercise) is that the delay for an adder to compute the carry out (from the carry-in, in the worst case) is fairly slow, and the second-stage adder cannot begin computingitscarry-out until the first-st...
2021-12-21 16:52:32
263
原创 HDLBits刷题_Verilog Language_Module fadd
In this exercise, you will create a circuit with two levels of hierarchy. Yourtop_modulewill instantiate two copies ofadd16(provided), each of which will instantiate 16 copies ofadd1(which you must write). Thus, you must writetwomodules:top_module...
2021-12-21 16:26:03
287
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