HDLBits刷题_Fsm1s

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1, but using synchronous reset.

解题思路：原代码中else的end位置给错，需要注意 

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    parameter A = 0, B = 1; // Fill in state name declarations

    reg present_state, next_state;
    
    always @(posedge clk) begin
        if (reset) begin  
            next_state = B;// Fill in reset logic
        end 
        
        else begin
            case (present_state)
                A: next_state = (in == 0) ? B : A;
                B: next_state = (in == 0) ? A : B;// Fill in state transition logic
            endcase
        end

            // State flip-flops
            present_state = next_state;   

            case (present_state)
                A: out = 0;
                B: out = 1;// Fill in output logic
            endcase
        //end
    end

endmodule