Synosys ahb vip环境与SINGLE,INCR,WRAP transaction 配置

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已于 2023-09-04 18:14:57 修改

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于 2023-09-04 17:32:38 首次发布

本文链接：https://blog.csdn.net/m0_69999886/article/details/132656089

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通过synosys ahb vip搭建1m/1s环境，并发起SINGLE，INCR，WRAP transaction，并发起先写后读测试。

发起single transaction的需要修改cust_svt_ahb_master_transaction.sv以及选择修改的ahb_master_directed_sequence.sv。transaction中有针对于random_sequence的constraint以及burst_type相应的权重，发起单一特定transaction并不需要，可以注释掉。

对于directed_sequence的修改：在原有配置的基础上，修改burst_type以及addr，burst_size一般配置为BURST_SIZE_32BIT，也就是4个Byte。地址的设置一般来说要与一次trans传输的总字节数相对应。在发送INCR4时，传输总字节数为4Byte×4beats=16Byte。

所以地址边界应该有这样的跳变 0×00 => 0×10 => 0×20 ......等等，transaction内部地址每次跳变4，基于以上，对sequence进行设置。

SINGLE和INCR略。

1.INCR4

for(int i = 0; i < sequence_length; i++) begin


      /** Set up the write transaction */
      `uvm_create(write_tran)
      write_tran.cfg          = cfg;
      
      `uvm_rand_send_with (write_tran,
        {  
          write_tran.xact_type    == svt_ahb_transaction::WRITE;
          write_tran.addr         == (32'h0000_0000 | ('h10 * i));
          write_tran.burst_type   == svt_ahb_transaction::INCR4;
          write_tran.burst_size   == svt_ahb_transaction::BURST_SIZE_32BIT;
          foreach (write_tran.data[i]) {
            write_tran.data[i] == i;
          }
        } ) 
      
      /** Wait for the write transaction to complete */
      get_response(rsp);

      `uvm_info("body", "AHB WRITE transaction completed", UVM_LOW);

      /** Set up the read transaction */
      `uvm_create(read_tran)
      read_tran.cfg          = cfg;
      
      `uvm_rand_send_with (read_tran,
        {  
          read_tran.xact_type    == svt_ahb_transaction::READ;
          read_tran.addr         == (32'h0000_0000 | ('h10 * i));
          read_tran.burst_type   == svt_ahb_transaction::INCR4;
          read_tran.burst_size   == svt_ahb_transaction::BURST_SIZE_32BIT;
        } )  
     
      /** Wait for the read transaction to complete */
      get_response(rsp);
    
      `uvm_info("body", "AHB READ transaction completed", UVM_LOW);

`uvm_rand_send_with用于指定随机化时的约束，transaction中的约束是SINGLE，INCR，以及INCR4所以sequence的约束burst_type类型如果是WRAP的话，就会出现error。可以在transaction中添加约束或者注释掉相关约束。

int burst_type_single_wt = 1;
    int burst_type_incr_wt = 1;
    int burst_type_incr4_wt = 1;
    int burst_type_incr8_wt = 1;
    int burst_type_incr16_wt = 1;
    int burst_type_wrap4_wt = 1;
    int burst_type_wrap8_wt = 1;
    int burst_type_wrap16_wt = 1;

  int num_busy_cycles_zero_wt = 500;
  int num_busy_cycles_non_zero_wt = 1;

  /** test delete if need */
  constraint master_constraints{
      burst_type dist{svt_ahb_transaction::SINGLE := burst_type_single_wt,
                      svt_ahb_transaction::INCR   := burst_type_incr_wt,
                      svt_ahb_transaction::INCR4  := burst_type_incr4_wt,
                      svt_ahb_transaction::INCR8  := burst_type_incr8_wt,
                      svt_ahb_transaction::INCR16 := burst_type_incr16_wt,
                      svt_ahb_transaction::WRAP4  := burst_type_wrap4_wt,
                      svt_ahb_transaction::WRAP8  := burst_type_wrap8_wt,
                      svt_ahb_transaction::WRAP16 := burst_type_wrap16_wt
                      };
    foreach (num_busy_cycles[i]) {
      num_busy_cycles[i] dist { 0 := num_busy_cycles_zero_wt, 
                                [1:16] := num_busy_cycles_non_zero_wt};  
                  }
              }
  /** UVM Object Utility macro */
  `uvm_object_utils_begin(cust_svt_ahb_master_transaction)
     `uvm_field_int(burst_type_single_wt,UVM_ALL_ON)
     `uvm_field_int(burst_type_incr_wt ,UVM_ALL_ON)
     `uvm_field_int(burst_type_incr4_wt ,UVM_ALL_ON)
     `uvm_field_int(burst_type_incr8_wt ,UVM_ALL_ON)
     `uvm_field_int(burst_type_incr16_wt ,UVM_ALL_ON)
     `uvm_field_int(burst_type_wrap4_wt ,UVM_ALL_ON)
     `uvm_field_int(burst_type_wrap8_wt ,UVM_ALL_ON)
     `uvm_field_int(burst_type_wrap16_wt ,UVM_ALL_ON)
  `uvm_object_utils_end

INCR4，四节拍递增突发波形图。htrans为2，NONSEQ，代表一次传输的起始。以及读出波形。

2.INCR8

INCR8，8拍递增突发，8beat×4Byte=32Byte，地址边界为0×00 => 0×20 => 0×40......。

for(int i = 0; i < sequence_length; i++) begin


      /** Set up the write transaction */
      `uvm_create(write_tran)
      write_tran.cfg          = cfg;
      
      `uvm_rand_send_with (write_tran,
        {  
          write_tran.xact_type    == svt_ahb_transaction::WRITE;
          write_tran.addr         == (32'h0000_0000 | ('h20 * i));
          write_tran.burst_type   == svt_ahb_transaction::INCR8;
          write_tran.burst_size   == svt_ahb_transaction::BURST_SIZE_32BIT;
          foreach (write_tran.data[i]) {
            write_tran.data[i] == i;
          }
        } ) 
      
      /** Wait for the write transaction to complete */
      get_response(rsp);

      `uvm_info("body", "AHB WRITE transaction completed", UVM_LOW);

      /** Set up the read transaction */
      `uvm_create(read_tran)
      read_tran.cfg          = cfg;
      
      `uvm_rand_send_with (read_tran,
        {  
          read_tran.xact_type    == svt_ahb_transaction::READ;
          read_tran.addr         == (32'h0000_0000 | ('h20 * i));
          read_tran.burst_type   == svt_ahb_transaction::INCR8;
          read_tran.burst_size   == svt_ahb_transaction::BURST_SIZE_32BIT;
        } )  
     
      /** Wait for the read transaction to complete */
      get_response(rsp);
    
      `uvm_info("body", "AHB READ transaction completed", UVM_LOW);