自己买了块开发板,准备在这个板子上从零开始做一些实验,记录一下实验结果。
开发板上LED灯电路如下:
给LED一个高电平,LED灯亮起,给LED低电平时,LED灯熄灭。
代码如下:
`timescale 1ns / 1ps
//
// Company:
// Engineer: Abshdbeh
//
// Create Date: 2023/06/21 18:53:03
// Design Name:
// Module Name: led
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module led(
input clk,
input rst,
output reg [3:0] led_o
);
localparam IDLE = 3'd0, //全灭
S0 = 3'd1, //LED0亮
S1 = 3'd2, //LED1亮
S2 = 3'd3, //LED2亮
S3 = 3'd4, //LED3亮
S4 = 3'd5; //全亮
localparam CNT_MAX = 'd100_000_000; //1s变化一次
reg [2:0] state;
reg [26:0] cnt; //1s count
always@(posedge clk or negedge rst)
if(!rst)
state <= IDLE;
else
case(state)
IDLE: if(cnt==CNT_MAX-1'b1) state <= S0;
S0: if(cnt==CNT_MAX-1'b1) state <= S1;
S1: if(cnt==CNT_MAX-1'b1) state <= S2;
S2: if(cnt==CNT_MAX-1'b1) state <= S3;
S3: if(cnt==CNT_MAX-1'b1) state <= S4;
S4: if(cnt==CNT_MAX-1'b1) state <= IDLE;
default: state <= IDLE;
endcase
always@(posedge clk or negedge rst)
if(!rst)
cnt <= 'd0;
else if(cnt==CNT_MAX-1'b1)
cnt <= 'd0;
else
cnt <= cnt+1'b1;
always@(posedge clk or negedge rst)
if(!rst)
led_o <= 4'b0000;
else
case(state)
IDLE: led_o <= 4'b0000;
S0: led_o <= 4'b0001;
S1: led_o <= 4'b0010;
S2: led_o <= 4'b0100;
S3: led_o <= 4'b1000;
S4: led_o <= 4'b1111;
default: led_o <= 4'b0000;
endcase
endmodule
连接好连线之后,将程序下载到板子上,进行测试,结果如下: