FPGA学习记录——实验三 PWM控制LED灯亮度

PWM(脉冲宽度调制)是一种使用数字信号控制模拟量的技术。

在本实验中通过改变1KHz周期方波的占空比，进而控制LED灯使其具有不同的亮度。

使用按键控制LED的亮度，按键消抖模块是为了消除按键的抖动。

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2023/06/28 19:33:08
// Design Name: 
// Module Name: key_filter
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module key_filter(
    input clk,
    input rst,
    input key,
    
    output reg key_en
    );
    
    reg key_d1;
    reg key_d2;
    reg [19:0] cnt; 
    
    always@(posedge clk or negedge rst)
        if(!rst)
            begin
                key_d1 <= 1'b0;
                key_d2 <= 1'b0;
            end
        else
            begin
                key_d1 <= key;
                key_d2 <= key_d1;
            end
            
    always@(posedge clk or negedge rst)
        if(!rst)
            cnt <= 'd0;
        else if(key_d2==1'b1)   
            cnt <= 'd0;
        else if(cnt=='d500_000)
            cnt <= cnt;
        else if(key_d2==1'b0)
            cnt <= cnt+1'b1;
            
    always@(posedge clk or negedge rst)
        if(!rst)
            key_en <= 1'b0;
        else if(cnt=='d499_999)
            key_en <= 1'b1;
        else
            key_en <= 1'b0;
    
endmodule

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2023/06/28 19:38:51
// Design Name: 
// Module Name: pwm_ctrl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module pwm_ctrl(
    input clk,
    input rst,
    input key_en,
    
    output [3:0] led_o
    );
    
    localparam IDLE = 2'd0,
               S0   = 2'd1,        
               S1   = 2'd2,        
               S2   = 2'd3;        
    
    reg [1:0] state;
    reg [12:0] pwm_cnt;
    reg pwm_w;
    
    always@(posedge clk or negedge rst)
        if(!rst)
            state <= IDLE;
        else
            case(state)
                IDLE:  if(key_en==1'b1) state <= S0;
                S0:  if(key_en==1'b1) state <= S1;
                S1:  if(key_en==1'b1) state <= S2;
                S2:  if(key_en==1'b1) state <= S0;
                default:  state <= IDLE;
            endcase
    
    always@(posedge clk or negedge rst)     //分频到1KHz
        if(!rst)
            pwm_cnt <= 'd0;
        else if(state==IDLE)
            pwm_cnt <= 'd0;
        else if(pwm_cnt=='d99_999)
            pwm_cnt <= 'd0;
        else
            pwm_cnt <= pwm_cnt+1'b1;
            
    always@(posedge clk or negedge rst)
        if(!rst)
            pwm_w <= 1'b0;
        else
            case(state)
                IDLE:  pwm_w <= 1'b0;
                S0:
                    begin
                        if(pwm_cnt<='d999)
                            pwm_w <= 1'b1;
                        else
                            pwm_w <= 1'b0;
                    end
                S1:
                    begin
                        if(pwm_cnt<='d3_999)
                            pwm_w <= 1'b1;
                        else
                            pwm_w <= 1'b0;
                    end
                S2:
                    begin
                        if(pwm_cnt<='d9_999)
                            pwm_w <= 1'b1;
                        else
                            pwm_w <= 1'b0;
                    end
                default:  pwm_w <= 1'b0;
            endcase
            
    assign led_o[0] = pwm_w;
    assign led_o[1] = pwm_w;
    assign led_o[2] = pwm_w;
    assign led_o[3] = pwm_w;
    
endmodule

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2023/06/28 19:52:47
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module top(
    input clk,
    input rst,
    input key,
    
    output [3:0] led_o
    );
    
    wire key_en;
    
    key_filter key_filter_inst(
    .clk        (clk),
    .rst        (rst),
    .key        (key),
    
    .key_en     (key_en)
    );
    
    pwm_ctrl pwm_ctrl(
    .clk        (clk   ),
    .rst        (rst   ),
    .key_en     (key_en),
                
    .led_o      (led_o)
    );
    
endmodule

实验结果如下：