library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Shift_Register is
Port (
CLK : in STD_LOGIC; -- 时钟输入
RESET : in STD_LOGIC; -- 复位输入
SHIFT_LEFT : in STD_LOGIC; -- 左移输入
SHIFT_RIGHT : in STD_LOGIC;-- 右移输入
PARALLEL_LOAD : in STD_LOGIC; -- 并行加载输入
DATA_IN : in STD_LOGIC_VECTOR(7 downto 0); -- 并行输入
DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0) -- 并行输出
);
end Shift_Register;
architecture Behavioral of Shift_Register is
signal reg : STD_LOGIC_VECTOR(7 downto 0); -- 寄存器
begin
process(CLK, RESET)
begin
if RESET = '1' then
reg <= (others => '0'); -- 同步复位
elsif rising_edge(CLK) then
if SHIFT_LEFT = '1' then
reg <= reg(6 downto 0) & '0'; -- 左移
elsif SHIFT_RIGHT = '1' then
reg <= '0' & reg(7 downto 1); -- 右移
elsif PARALLEL_LOAD = '1' then
reg <= DATA_IN; -- 并行加载
end if;
end if;
end process;
DATA_OUT <= reg; -- 并行输出
end Behavioral;