AXI_DMAC的寄存器说明

来自:https://wiki.analog.com/resources/fpga/docs/hdl/regmap#folded_1ef0a96bdee03491ff600d93e2c50767_1

这里是ADI提供的DMAC,不是XILINX的VIVADO自带的。请注意区分!

 

 

 

 

AddressBitsNameTypeDefaultDescription 
DWORD 
0x000VERSIONVersion of the peripheral. Follows semantic versioning. Current version 4.02.61. 
 [31:16]VERSION_MAJORRO0x04  
[15:8]VERSION_MINORRO0x02  
[7:0]VERSION_PATCHRO0x61  
0x001PERIPHERAL_ID  
 [31:0]PERIPHERAL_IDROIDValue of the ID configuration parameter. 
0x002SCRATCH  
 [31:0]SCRATCHRW0x00000000Scratch register useful for debug. 
0x003IDENTIFICATION  
 [31:0]IDENTIFICATIONRO0x444D4143Peripheral identification ('D', 'M', 'A', 'C'). 
0x020IRQ_MASK  
 [1]TRANSFER_COMPLETEDRW0x1Masks the TRANSFER_COMPLETED IRQ. 
[0]TRANSFER_QUEUEDRW0x1Masks the TRANSFER_QUEUED IRQ. 
0x021IRQ_PENDING  
 [1]TRANSFER_COMPLETEDRW1C0x0This bit will be asserted if a transfer has been completed and the TRANSFER_COMPLETED bit in the IRQ_MASK register is not set. Either if all bytes have been transferred or an error occurred during the transfer. 
[0]TRANSFER_QUEUEDRW1C0x0This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. It can be masked out by setting the TRANSFER_QUEUED bit in theIRQ_MASK register. 
0x022IRQ_SOURCE  
 [1]TRANSFER_COMPLETEDRO0x0This bit will be asserted if a transfer has been completed. Either if all bytes have been transferred or an error occurred during the transfer. Cleared together with the corresponding IRQ_PENDING bit. 
[0]TRANSFER_QUEUEDRO0x0This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. Cleared together with the corresponding IRQ_PENDING bit. 
0x100CONTROL  
 [1]PAUSERW0x0When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again. 
[0]ENABLERW0x0When set to 1 the DMA channel is enabled. 
0x101TRANSFER_ID  
 [4:0]TRANSFER_IDRO0x00This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_SUBMIT is 0. 
0x102TRANSFER_SUBMIT  
 [0]TRANSFER_SUBMITRW0x00Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been queued or the DMAchannel is disabled. Writing a 0 to this register has no effect. 
0x103FLAGS  
 [0]CYCLICRWCYCLICSetting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode the controller will re-start a transfer again once it has finished. In cyclic mode no end-of-transfer interrupts will be generated. 
[1]TLASTRW0x1When setting this bit for a MM to AXIS transfer the TLAST signal will be asserted during the last beat of the transfer. For AXIS to MM transfers the TLAST signal from the AXIS interface is monitored. After its occurrence all descriptors are ignored until this bit is set. 
[2]PARTIAL_REPORTING_ENRW0x0When setting this bit the length of partial transfers caused eventually by TLAST will be recorded. 
[3]FRAME_LOCK_ENRW0x0When setting this bit the module will operate in frame lock mode. 
0x104DEST_ADDRESS  
 [31:0]DEST_ADDRESSRW0x00000000This register contains the destination address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for write to memory support. 
0x105SRC_ADDRESS  
 [31:0]SRC_ADDRESSRW0x00000000This register contains the source address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for read from memory support. 
0x106X_LENGTH  
 [23:0]X_LENGTHRW{log2(max(Number of bytes to transfer - 1. 
DMA_DATA_WIDTH_SRC, 
DMA_DATA_WIDTH_DEST 
)/8){1'b1}} 
0x107Y_LENGTH  
 [23:0]Y_LENGTHRW0x000000Number of rows to transfer - 1. Note, this field is only valid if the DMA channel has been configured with 2D transfer support. 
0x108DEST_STRIDE  
 [23:0]DEST_STRIDERW0x000000The number of bytes between the start of one row and the next row for the destination address. Needs to be aligned to the bus width. Note, this field is only valid if the DMAchannel has been configured with 2D transfer support and write to memory support. 
0x109SRC_STRIDE  
 [23:0]SRC_STRIDERW0x000000The number of bytes between the start of one row and the next row for the source address. Needs to be aligned to the bus width. Note, this field is only valid if the DMAchannel has been configured with 2D transfer and read from memory support. 
0x10aTRANSFER_DONEIf bit x is set in this register the transfer with ID x has been completed. The bit will automatically be cleared when a new transfer with this ID is queued and will be set when the transfer has been completed. 
 [0]TRANSFER_0_DONERO0x0If this bit is set the transfer with ID 0 has been completed. 
[1]TRANSFER_1_DONERO0x0If this bit is set the transfer with ID 1 has been completed. 
[2]TRANSFER_2_DONERO0x0If this bit is set the transfer with ID 2 has been completed. 
[3]TRANSFER_3_DONERO0x0If this bit is set the transfer with ID 3 has been completed. 
[31]PARTIAL_TRANSFER_DONERO0x0If this bit is set at least one partial transfer was transferred. This field will reset when the ENABLE control bit is reset or when all information on partial transfers was read through PARTIAL_TRANSFER_LENGTH and PARTIAL_TRANSFER_ID registers. 
0x10bACTIVE_TRANSFER_ID  
 [4:0]ACTIVE_TRANSFER_IDRO0x00ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register. 
0x10cSTATUS  
 [31:0]RESERVEDRO0x00This register is reserved for future usage. Reading it will always return 0. 
0x10dCURRENT_DEST_ADDRESS  
 [31:0]CURRENT_DEST_ADDRESSRO0x00Address to which the next data sample is written to. This register is only valid if the DMA channel has been configured for write to memory support. 
0x10eCURRENT_SRC_ADDRESS  
 [31:0]CURRENT_SRC_ADDRESSRO0x00Address form which the next data sample is read. This register is only valid if the DMAchannel has been configured for read from memory support. 
0x112TRANSFER_PROGRESS  
 [23:0]TRANSFER_PROGRESSRO0x000000This field presents the number of bytes transferred to the destination for the current transfer. This register will be cleared once the transfer completes. This should be used for debugging purposes only. 
0x113PARTIAL_TRANSFER_LENGTH  
 [31:0]PARTIAL_LENGTHRO0x000000Length of the partial transfer in bytes. Represents the number of bytes received until the moment of TLAST assertion. This will be smaller than the programmed length from the X_LENGTH and Y_LENGTH registers. 
0x114PARTIAL_TRANSFER_IDMust be read after the PARTIAL_TRANSFER_LENGTH registers. 
 [1:0]PARTIAL_TRANSFER_IDRO0x0ID of the transfer that was partial. 
0x115FRAME_LOCK_CONFIG  
 [5:0]FLOCK_NUMFRAMESRW0x00Number of frame buffers to cycle through. Valid range 1..MAX_NUM_FRAMES synthesis parameter. 
[8]FLOCK_MODERW0x00 - Dynamic mode. In this mode the writer DMA (s2mm) will not step on the currently read buffer. In this mode the reader DMA(mm2s) will always read the most recent complete buffer. To be used in any-to-any frame rate adaptation applications. 1 - Simple mode. In this mode the writer will cycle through MAX_NUM_FRAMES buffers without caring about the reader. The reader will stay behind the writer with a predefined number of buffers described by FLOCK_FRAMEDISTANCE field. To be used in applications with similar read-write frame rate, to induce a programmed frame delay between writer and reader. 
[9]FLOCK_WAIT_WRITERRW0x0This field is valid only if the core is configured in reader mode (mm2s configuration). 0 - In this mode, once the core is enabled the reader will start to access a buffer immediately without the writer filled it first, resulting in outputting random data. 1 - In this mode, once the core is enabled the reader will wait the master to fill FLOCK_FRAMEDISTANCE+1 buffers before starting to read it. This ensures a smooth start without reading invalid data from the buffers. During the wait period external synchronization requests are ignored. 
[20:16]FLOCK_FRAMEDISTANCERW0x00Number of frames the reader DMA (mm2s) will stay behind the writer DMA minus one. Valid only when DMAC is in reader mode, it is in simple flock mode (FLOCK_MODE is 1) and FRAME_LOCK_EN bit from FLAGS register is set. Valid range 0..FLOCK_NUMFRAMES-2 e.g 0 - Reader will operate on the latest available buffer.; FLOCK_NUMFRAMES-2 - Reader will operate on the oldest available buffer. 
0x116FRAME_LOCK_STRIDE  
 [31:0]FLOCK_FRAMESTRIDERW0x00Stride of consecutive frames in memory in bytes. Should be at least the size of one frame (X_LENGTH+1) * (Y_LENGTH+1); 
       

 

 

 

 

 

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