延迟复位模块

module syn_rst_dly(
input rst_i,clk,
output rst_o
)
parameter RST_SYNC_NUM  =  25 ;
reg [RST_SYNC_NUM-1:0]rst0_sync_r ;


  always @(posedge clk0_bufg or posedge rst_tmp)
    if (rst_i)
      rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
    else
      // logical left shift by one (pads with 0)
      rst0_sync_r <= rst0_sync_r << 1;
assign rst_o  = rst0_sync_r[RST_SYNC_NUM-1];


endmodule