PMODAD1 实现模拟数据的采集实现篇1

最新推荐文章于 2022-06-14 21:43:06 发布

mcupro

最新推荐文章于 2022-06-14 21:43:06 发布

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分类专栏： ZYNQ7 OV7670 FPGA VERILOG ZYNQ7 总结和计划 ZEDBOARD

本文链接：https://blog.csdn.net/mcupro/article/details/74001677

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从硬件篇我们看到一个PMOD模块包含了两路ADC，他们公用SCLK和CSN，只是有两路各自的DATA输出，因此我们将采集模块简单修改一下，能同时采集两路，如下：

module ad7476_sample(
        input clk,rst,
        input  ADC_sdata0, ADC_sdata1,
        output reg ADC_sclk,ADC_csn,
        output reg [11:0]  adc_res0, adc_res1,
        output reg   adc_valid
    );

    reg [7:0] cntr ;
    always @ (posedge clk) //clk 35MHZ
        if (rst)cntr<=0;else if (cntr == 34) cntr<=0;else cntr<=cntr+1;


    always @ (posedge clk)
    case (cntr )
        0:  ADC_csn <= 0;
        33:  ADC_csn <= 1;
    endcase

    always @ (posedge clk)
    case (cntr)
        //0,1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,34 :
        34,0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,33 :ADC_sclk<=1;
        default ADC_sclk<=0;
    endcase

    always @ (posedge clk)
    case (cntr )
        8: adc_res0[11] <= ADC_sdata0 ;
        10:adc_res0[10] <= ADC_sdata0 ;
        12:adc_res0[9] <= ADC_sdata0 ;
        14:adc_res0[8] <= ADC_sdata0 ;
        16:adc_res0[7] <= ADC_sdata0 ;
        18:adc_res0[6] <= ADC_sdata0 ;
        20:adc_res0[5] <= ADC_sdata0 ;
        22:adc_res0[4] <= ADC_sdata0 ;
        24:adc_res0[3] <= ADC_sdata0 ;
        26:adc_res0[2] <= ADC_sdata0 ;
        28:adc_res0[1] <= ADC_sdata0 ;
        30:adc_res0[0] <= ADC_sdata0 ;
    endcase




    always @ (posedge clk)
    case (cntr )
        8: adc_res1[11] <= ADC_sdata1 ;
        10:adc_res1[10] <= ADC_sdata1 ;
        12:adc_res1[9] <= ADC_sdata1 ;
        14:adc_res1[8] <= ADC_sdata1 ;
        16:adc_res1[7] <= ADC_sdata1 ;
        18:adc_res1[6] <= ADC_sdata1 ;
        20:adc_res1[5] <= ADC_sdata1 ;
        22:adc_res1[4] <= ADC_sdata1 ;
        24:adc_res1[3] <= ADC_sdata1 ;
        26:adc_res1[2] <= ADC_sdata1 ;
        28:adc_res1[1] <= ADC_sdata1 ;
        30:adc_res1[0] <= ADC_sdata1 ;
    endcase


    always @ (posedge clk)adc_valid <= cntr == 32 ;


endmodule

我们将PMOD插入JA1，如下图：

直接从图上可以看出引脚对应

CSN->JA1

D0->JA2

D1->JA3

CLK->JA4

之后我们再找找JA引脚对应关系，我在这里拷贝一下：

# PMOD JA

set_property  -dict {PACKAGE_PIN Y11   IOSTANDARD LVCMOS33} [get_ports pmod_ja1];
set_property  -dict {PACKAGE_PIN AA11  IOSTANDARD LVCMOS33} [get_ports pmod_ja2];
set_property  -dict {PACKAGE_PIN Y10   IOSTANDARD LVCMOS33  PULLUP true} [get_ports pmod_ja3];
set_property  -dict {PACKAGE_PIN AA9   IOSTANDARD LVCMOS33} [get_ports pmod_ja4];
set_property  -dict {PACKAGE_PIN AB11  IOSTANDARD LVCMOS33} [get_ports pmod_ja7];
set_property  -dict {PACKAGE_PIN AB10  IOSTANDARD LVCMOS33} [get_ports pmod_ja8];
set_property  -dict {PACKAGE_PIN AB9   IOSTANDARD LVCMOS33} [get_ports pmod_ja9];
set_property  -dict {PACKAGE_PIN AA8   IOSTANDARD LVCMOS33} [get_ports pmod_ja10];

# PMOD JB

set_property  -dict {PACKAGE_PIN W12   IOSTANDARD LVCMOS33} [get_ports pmod_jb1];
set_property  -dict {PACKAGE_PIN W11   IOSTANDARD LVCMOS33} [get_ports pmod_jb2];
set_property  -dict {PACKAGE_PIN V10   IOSTANDARD LVCMOS33  PULLUP true} [get_ports pmod_jb3];
set_property  -dict {PACKAGE_PIN W8    IOSTANDARD LVCMOS33} [get_ports pmod_jb4];
set_property  -dict {PACKAGE_PIN V12   IOSTANDARD LVCMOS33  PULLDOWN true} [get_ports pmod_jb7];
set_property  -dict {PACKAGE_PIN W10   IOSTANDARD LVCMOS33  PULLDOWN true} [get_ports pmod_jb8];
set_property  -dict {PACKAGE_PIN V9    IOSTANDARD LVCMOS33  PULLDOWN true} [get_ports pmod_jb9];
set_property  -dict {PACKAGE_PIN V8    IOSTANDARD LVCMOS33  PULLDOWN true} [get_ports pmod_jb10];

# PMOD JC

set_property  -dict {PACKAGE_PIN AB7   IOSTANDARD LVCMOS33} [get_ports pmod_jc1];
set_property  -dict {PACKAGE_PIN AB6   IOSTANDARD LVCMOS33} [get_ports pmod_jc2];
set_property  -dict {PACKAGE_PIN Y4    IOSTANDARD LVCMOS33  PULLUP true} [get_ports pmod_jc3];
set_property  -dict {PACKAGE_PIN AA4   IOSTANDARD LVCMOS33} [get_ports pmod_jc4];
set_property  -dict {PACKAGE_PIN R6    IOSTANDARD LVCMOS33} [get_ports pmod_jc7];
set_property  -dict {PACKAGE_PIN T6    IOSTANDARD LVCMOS33} [get_ports pmod_jc8];
set_property  -dict {PACKAGE_PIN T4    IOSTANDARD LVCMOS33} [get_ports pmod_jc9];
set_property  -dict {PACKAGE_PIN U4    IOSTANDARD LVCMOS33} [get_ports pmod_jc10];

# PMOD JD

set_property  -dict {PACKAGE_PIN V7    IOSTANDARD LVCMOS33} [get_ports pmod_jd1];
set_property  -dict {PACKAGE_PIN W7    IOSTANDARD LVCMOS33} [get_ports pmod_jd2];
set_property  -dict {PACKAGE_PIN V5    IOSTANDARD LVCMOS33  PULLUP true} [get_ports pmod_jd3];
set_property  -dict {PACKAGE_PIN V4    IOSTANDARD LVCMOS33} [get_ports pmod_jd4];
set_property  -dict {PACKAGE_PIN W6    IOSTANDARD LVCMOS33  PULLDOWN true} [get_ports pmod_jd7];
set_property  -dict {PACKAGE_PIN W5    IOSTANDARD LVCMOS33} [get_ports pmod_jd8];
set_property  -dict {PACKAGE_PIN U6    IOSTANDARD LVCMOS33} [get_ports pmod_jd9];
set_property  -dict {PACKAGE_PIN U5    IOSTANDARD LVCMOS33} [get_ports pmod_jd10];

因此我们对应完善一下PMODAD1引脚映射

CSN->JA1->Y11

D0->JA2->AA11

D1->JA3->Y10

CLK->JA4 ->AA9

另外我们将采集到的数值用LED显示，由于只有8位LED，因此我们之考虑显示高8位。上层代码如下：

     
module PMODAD_LED(
        input clk,sw0,
        output  reg  [7:0] LED  ,
        input  ADC_sdata0, ADC_sdata1,
        output  ADC_sclk,ADC_csn
    );


    wire clk35M ;


    design_1_wrapper uu(
                         .clk_in1( clk ) ,
                         .clk_out1( clk35M )
                     );

    wire   [11:0]  adc_res0, adc_res1;
    wire     adc_valid;
    always @ (posedge clk35M)if (adc_valid) LED <= ( sw0 == 1 )  ?  adc_res0[11:4]   :  adc_res1[11:4]  ;

    ad7476_sample  u1(
                       .clk( clk35M )  ,
                       .rst( 1'b0 )  ,
                       .ADC_sdata0(ADC_sdata0  )  ,
                       .ADC_sdata1(ADC_sdata1  )  ,
                       .ADC_sclk(ADC_sclk  )  ,
                       .ADC_csn(ADC_csn  )  ,
                       .adc_res0(adc_res0  )  ,
                       .adc_res1(adc_res1  )  ,
                       .adc_valid(adc_valid  )
                   );

endmodule

这里使用了一个sw0来切换两路显示。

引脚约束文件如下：

set_property PACKAGE_PIN Y9 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]

set_property PACKAGE_PIN F22 [get_ports {sw0}]
set_property IOSTANDARD LVCMOS18 [get_ports {sw0}] 

set_property PACKAGE_PIN T22 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]

set_property PACKAGE_PIN T21 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]

set_property PACKAGE_PIN U22 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]

set_property PACKAGE_PIN U21 [get_ports {LED[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]

set_property PACKAGE_PIN V22 [get_ports {LED[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
set_property PACKAGE_PIN W22 [get_ports {LED[5]}]

set_property PACKAGE_PIN U19 [get_ports {LED[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]

set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
set_property PACKAGE_PIN U14 [get_ports {LED[7]}]


set_property  -dict {PACKAGE_PIN Y11   IOSTANDARD LVCMOS33} [get_ports ADC_csn];
set_property  -dict {PACKAGE_PIN AA11  IOSTANDARD LVCMOS33} [get_ports ADC_sdata0];
set_property  -dict {PACKAGE_PIN Y10   IOSTANDARD LVCMOS33  } [get_ports ADC_sdata1];
set_property  -dict {PACKAGE_PIN AA9   IOSTANDARD LVCMOS33} [get_ports ADC_sclk];

下载到ZEBBOARD板子运行，一切正常，输入不同电压值，8个LED作为高8位会有数值的变化。

实验就成功了。另外如果有兴趣的话，可以考虑用ILA连续观测采集电压输入波形。