module adder(A,B,C); //output C=A+B C={1'b,13'b}={sign,value}
input CLK;
input RST;
input signed [15:0] A,B;//input parameter A={1'b,12'b}={sign,value}
//B={1'b,12'b}={sign,value}
output signed [16:0] C;
reg [16:0] c;
always @(posedge CLK,negedge RST)
if(!RST)begin
c<=17'b0;
end else begin
if(A[15]==0&&B[15]==0)begin //if(A is positive and B is positive )
c<={1'b0,{1'b0,A[14:0]}+{1'b0,B[14:0]}};
end
if(A[15]==1&&B[15]==0)begin //if(A is negative and B is positive )
if(A[14:0]>B[14:0]) c<={1'b1,{1'b0,A[14:0]}-{1'b0,B[14:0]}};
else c<={1'b0,{1'b0,B[14:0]}-{1'b0,A[14:0]}};
end
if(A[15]==0&&B[15]==1)begin //if(A is positive and B is negative )
if(A[14:0]>B[14:0]) c<={1'b0,{1'b0,A[14:0]}-{1'b0,B[14:0]}};
else c<={1'b1,{1'b0,B[14:0]}-{1'b0,A[14:0]}};
end
if(A[15]==1&&B[15]==1)begin //if(A is negative and B is negative )
c<={1'b1,{1'b0,A[14:0]}+{1'b0,B[14:0]}};
end
end
assign C=c;
endmodule