verilog实现16bit超前进位加法器

 //16位
 module Add16_head
 (
	input [15:0]A,
	input [15:0]B,
	input C_in,
	output [15:0] F,
	output Gm,
	output Pm,
	output C_out
 );
 wire [3:0]G;
 wire [3:0]P;
 wire [4:1]C;
Add4_head A0
 (
	.A(A[3:0]),
	.B(B[3:0]),
	.C_in(C_in),
	.F(F[3:0]),
	.Gm(G[0]),
	.Pm(P[0])
 );
 Add4_head A1
 (
	.A(A[7:4]),
	.B(B[7:4]),
	.C_in(C[1]),
	.F(F[7:4]),
	.Gm(G[1]),
	.Pm(P[1])
 );
 Add4_head A3
 (
	.A(A[11:8]),
	.B(B[11:8]),
	.C_in(C[2]),
	.F(F[11:8]),
	.Gm(G[2]),
	.Pm(P[2])
 );
 Add4_head A4
 (
	.A(A[15:12]),
	.B(B[15:12]),
	.C_in(C[3]),
	.F(F[15:12]),
	.Gm(G[3]),
	.Pm(P[3])
 );
  CLA_4 AAt
 (
	.P(P),
	.G(G),
	.C_in(C_in),
	.Ci(C),
	.Gm(Gm),
	.Pm(Pm)
 );
 assign C_out=C[4];
 endmodule

  这里把一个4位全加器当做一个1bit的来用，4个连在一起，通过一个cla_4实现超前进位