jtag菊花链拓扑

关于XilinxFPGA JTAG下载时菊花链路中的芯片数量

当一个系统中含有多片（2片以上）XilinxFPGA、CPLD或PROM（FLASH）时，可采用单一JTAG口以菊花链（Daisy Chain）形式将所有芯片串联起来实现下载编程，如下图所示。这样做有两个好处：（1）可以节省多个JTAG口所占用的PCB空间，特别适合空间有限的嵌入式系统，如小型工业摄像机等；（2）嵌入式系统处于封闭环境中，有时需要对系统中的FPGA程序进行在线或远程升级，必须将JTAG口引到机箱外，显然这种单JTAG口的菊花链结构是最佳选择。

1、关于链路中的芯片数量

Xilinx的UG380：“Spartan-6FPGA Configuration User Guide”的第58页“JTAG Signal Routing”一节有如下描述：

The TCK and TMSsignals go to all devices in the chain; consequently, their signal quality

is important. For example, TCK should transition monotonicallyat all receivers to ensure

proper JTAG functionality and must be properlyterminated. The quality of TCK can limit

the maximum frequency for reliable JTAG configuration.

Additionally, if thechain is large (three devices or more), TMS and TCK should be buffered

to ensure that they have sufficient drive strength at allreceivers, and the voltage at logic

High must be compatible with all devices in the chain.

由于TCK和TMS两个信号是连接到菊花链中的所有芯片，因此这两个信号的质量（完整性）非常重要！特别是时钟信号TCK，任何毛刺干扰和边沿抖动都会导致下载失败。

当菊花链中的芯片（或设备）在3个以上时，TMS和TCK必须加缓冲器（如74LVC245），以增加其驱动能力，对于一些驱动能力差的国产下载器尤其重要。每个驱动门所在分支链路中的芯片（或设备）数量取决于缓冲器的驱动能力，一般74LVC245(8缓冲)的一个缓冲门可驱动3~4个负载（芯片）。在TCK的缓冲器输出端串接一个20~30Ω的电阻，设备端并接一个100~1000p的电容到地，可明显降低边沿抖动、减少毛刺干扰。

TMS是一个模式选择开关信号，TCK是时钟脉冲信号，缺省频率为6MHz，当负载较多时，不加缓冲适当降低TCK的频率也可提高信号完整性。

       JTAG协议规定TCK下降沿输出TDI数据有效，并在TCK上升沿采集TDO数据，因此，在整个JTAG链中必须保证TDI至TDO的贯通延时（Propagation Delay）T_CPD必须小于TCK的1/2周期T_CLK/2，即△T=T_CLK/2 –T_CPD>0。也就是说，在增加缓冲驱动的情况下，JTAG链路中的芯片总数与每个芯片的TDO延时T_DOV（FPGA为T_TCKTDO）和TCK频率有关。在芯片总数确定以后，为保证△T>0，可以降低TCK的频率。

       下面举一个实例：假设一个封闭嵌入式系统中有三个模块（或电路板）：B1、B2、B3，其中B1、B2的JTAG分支都含1片XCF16P PROM、1片V5 FPGA；B3的JTAG分支含1片XCF16P PROM、1片V5 FPGA、1片S6 FPGA外挂1片8M SPI FPASH。 三个模块的TDI、TDO按B1→B2→B3顺序串接；外部接1个JTAG口，其TCK、TMS在母板上经3路缓冲驱动（74LVC1T45）分别至每个模块，TCK串接22Ω电阻。整个JTAG链上串联7个芯片（不算SPI），其中3个XCF16P、3个V5、1个S6，总的T_CPD =3×22+3×6+6.5=85.5ns。考虑到缓冲器和线路延时，T_CPD>100ns，因此TCK频率取3MHz最合适，其T_CLK/2 =167ns。

 

2、如何设置JTAG的TCK频率

启动Xilinx FPGA/PROM下载工具iMpact，点击“Output| Cable Setup…”，下拉“TCK Speed/Baud Rate：”设置频率，缺省值为6MHz，如下图所示：

 

3、补充：

JTAG的拓扑比较诡异，尽管频率不高。 
TMS、TCK是一主多从并联的结构；TDI、TDO是一主一从串联的。 
如果板上没有TMS、TCK的缓冲器，且布局布线不够好，TCK上的过冲会厉害， 
只要过冲造成一个错误的边沿，JTAG就挂了。 

解决办法就是降低TCK的频率，线上串小电阻，TCK/TMS终端并个小电容。

 

4、Question：

 1）. We areusing 2 Vertex 5 & spartan 6 FPGA'S , configuring all FPGA's through daisy chain mode selection, as per fpga user guidedatasheet we provided the option for daisy chain.

2）. Daisy chain configuraion we provided in Mainboard, now we need to extend this daisy chain  configuration  to the Front panel daughter card.samecircuitry we used in Front panel Baord aslo ,from main board to Front panelboard we need a cable of FRC 15".

3）.From mainboard to front panel board we are using  the 14 pin FRC Cable as acommunication cable.

4）. The jumperselection for daisy chain configuration through Front paneldaughter card, we are observing inconsistency in FPGA chain detection.

Samething we implented in Main Board & frontpanel Board, in between we are using the FRC cable of lenght 15".  Daisy chain is not detecting properly , itsdetecting only one FPGA .

 

Answer：

Youneed to look at the signal integrity, especially for the TCK signal. Other signals are not as important as long as you can reduce theconfiguration frequency.  However the TCKsignal can not tolerate ringing and should be routed with this inmind.  Since you have loads on a main board, then a cable, then loads onanother board, you should probably use a buffer on the main boardfor TCK (at that point you might as well buffer TDI and TMS as well). Use ground-signal-ground on the ribbon cable to provide a reasonableimpedance.  Then select a source series termination resistorat the buffer which provides the best signal integrity when seen at the load onthe remote board.  Ideally you'd want to do this for all signals, but as Isaid you can get away with just TCK as long as you arewilling to slow down the configuration clock. Note that reducingthe clock rate will not help if yourTCK has sufficient ringing at the load to cause multiple edges per clockperiod.

 

Ifyou already have a system and want to try a band-aid fix, you could try to justadd a small capacitor at the TCK pin of the part on the remoteboard to see if that reduces the ringing enough to enable a cleanconfiguration.