mikiah的专栏

1.验证目录结构的建立要实现验证自动化，首先要建立一个科学的验证目录，这是实现验证自动化的基础，具体目录如下图所示：图1验证目录结构图如上图所示Verification为一个总目录，其下包含九个子目录，regress目录用于存放回归验证所产生的日志，其中包含一个regression．log文件，其主要内容为显示每条testcase通过与否；coverage目录用于存放代码覆盖率文件；log目录用于存放每条case产生的日志；run目录中存放run脚本，包括运行每一条case的脚本run和运行回归验证的脚本r

VMM has two types of generators. Atomic generator and Scenario generator.Atomic generator is a simple generator which generates transactions randomly.`vmm_atomic_gen is a macro which is us

Callback mechanism is used for altering the behavior of the transactor without modifying the transactor. One of the many promises of Object-Oriented programming is that it will allow for plug-and-play

VMM复习手记(2011-03-21 19:35:43) 标签：杂谈分类： tech1. 使用VMM的库文件：`include "vmm.sv"2. 基类和派生类指针引用：例如class packet;class packet_new extends packet;packet p;packet_n

Verification environment is developed by extending vmm_env class.  The TestBench simulation needs some systematic flow like reset, initialize etc. vmm_env base class has methods formalize the simulati

VMM DATAvmm_data class is to be used to model all transactions in the infrastructure . It provides a standard set of methods expected to be found in all transactions. All transactions in the ver

Atomic generator generates individual data items or transaction descriptors. Each item is generated independently of other items in a random fashion. Atomic generator is simple to describe and use.

function bit [15:0] compute_crc16(const ref logic [7:0] bytes[],                                                input int unsigned    offset = 0,                                                inp

vmm_test is introduced in vmm 1.1. To know the vmm version which you are using, use this commandvcs -R -sverilog -ntb_opts dtm          +incdir+$VMM_HOME/sv $VMM_HOME/sv/vmm_versions.svv

1.fork join           2.使用rand_mode()禁止随机变量rand_mode()方法能用于控制随机变量是否有效。当一个随机变量是被禁止的时候，如同没有被声明为rand或者randc一样。无效变量不会被randomize()方法随机化，它们的值等同非随机变量，也称为状态变量。所有的随机变量初始都是有效、使能的。ran

//测试平台`timescale 1ns/1psmodule tb(); reg clk; reg clk4; reg por; reg din_100; reg din_10; reg rx_en; wire din_w; wire din; wire din_100_en;

Code coverage is a technology that can identify what code has been(and more importantly not been) executed in the design under verification.

1.下图是基本测试平台的结构               2.verification harness Instead of a monolithic block, the testbenches shoul

Writing testbenches involves writing a lot of code and also requires coding guidelines. These guidelines are designed to enhance code mainta

验证计划的技术需求分为：验证层次的描述、待验证的功能、细节测试及方法、覆盖率需求、测试场景（矩阵）验证计划的工程管理部分有：必需的工具、风险和依赖、资源需求、进度细节。1.验证层次的描述验证团队在验证一个设计时所做的第一个决定就是弄清楚验证层次。系统可能包含很多设计层次，根据每个层次的复杂度，验证团队必须决定是独立的验证每个层次，还是按功能

First ,verification plan --------a specification of the functioal verification process and  of the testbench infrastructure that will be necessary to support it.It is used to define what is first-time success,how a design is verified and which testbenches

本篇文章介绍命令层主动事务处理器的编写方法。命令层事务处理器就是一个一端是事务级接口，一端连接物理信号，也称为BFM。如图所示： 第一步：第二步：第三步：事务描述符（同命令层监视器）第四步：主动事务处理器现在开始写主动性事务处理器，它是由vmm_xacto

1. several ways to sample output signalalways @(negedge clk)begin $strobe(...)endparameter INTERVAL = 10;alwaysbegin #

1. clock signalGenerate the clock signals using a module thread. Program threads are designed to be reactive to the events occurring in th

第一步：接口第一步定义在主设备和从设备之间交换信息的物理接口信号。单个信息交换（读或写操作）称为一个事务。在APB总线上只有一个主设备，可以有多个从从设备。从设备根据不同的地址范围来区分。信号是在接口中定义的。接口的名字以前缀"apb_"开始，以此来鉴别接口遵循APB协议

1.总线功能模型作用：总线功能模型可以用来产生激励，也可以监视设计的响应。通常，一个总线功能模型实现这两个操作。2.CPU transactions              task write_cycle

the purpose of BFM is to remove the testbench from repetitive physical level details.

设计组件可以用事务处理器来代替。嵌入式RAM块可以用从动性事务处理起来代替。程序存储器接口的总线功能模型就是从动性事务处理器。DUT发出一个写命令，然后总线功能模型则把数据写到块内RAM的关联数组内；DUT发出一个读命令，则从动性事务处理器把相应地址的数据发送出去。上图中的RAM

2000年, Verisity Design（现在的Cadence Design System公司）引进了Verification Advisor（vAdvisor）采用了e语言，包含了激励的产生，自动比对的策略，覆盖率模型。e语言是面向对象语言，这是业界开始使用面向对象语言进行测试平台的建立。2002年，Verisity公司公布了第一个验证库——e可重用方法学（eRM）。 2003年