//测试平台
`timescale 1ns/1ps
module tb();
reg clk;
reg clk4;
reg por;
reg din_100;
reg din_10;
reg rx_en;
wire din_w;
wire din;
wire din_100_en;
wire din_10_en;
wire rst;
zdvc_vcd_interface m(
.clk(clk),
.clk4(clk4),
.por(por),
.din_100(din_100),
.din_10(din_10),
.rx_en(rx_en),
.din_w(din_w),
.din(din),
.din_100_en(din_100_en),
.din_10_en(rst)
);
initial
begin
$fsdbDumpfile("wave_test.fsdb");
$fsdbDumpvars;
end
//always #147.5 clk4 = ~clk4;
initial
begin
clk = 1'b0;
fork:genclk4
begin
forever #147.5 clk4 = ~clk4;
end
join_none
por = 1'b0;
clk4 = 1'b0;
din_100 = 1'b1;
din_10 = 1'b1;
rx_en = 1'b0;
# 590
por = 1'b1;
# 2360;
din_100 = 1'b0;
#47 din_100 = 1'b1;
#120 din_100 = 1'b0;
#100 din_100 = 1'b1;
#230 din_100 = 1'b0;
#200 din_100 = 1'b1;
#67 din_100 = 1'b0;
#120 din_100 = 1'b1;
#65 din_100 = 1'b0;
disable genclk4;
clk4 = 1'b0;
#5000 din_100 = 1'b1;
fork:gen2clk4
begin
forever #147.5 clk4 = ~clk4;
end
join_none
#66 din_100 = 1'b0;
#122 din_100 = 1'b1;
#80 din_100 = 1'b0;
#21 din_100 = 1'b1;
#83 din_100 = 1'b0;
#230 din_100 = 1'b1;
#3300 din_100 = 1'b1;
$stop;
end
endmodule
源代码//省略,呵呵,
波形可以看看哦,