程序设计与仿真
电子琴VHDL程序包含有:顶层程序、音阶发生器程序、数控分频模块程序和自动演奏模块程序。
1.顶层程序与仿真
(1)顶层VHDL程序
--文件名:top.vhd
--功能:顶层文件
--最后修改日期:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( clk32MHz :in std_logic; --32MHz系统时钟
handTOauto : in std_logic; --键盘输入/自动演奏
code1 :out std_logic_vector(6 downto 0); --音符显示信号
index1 :in std_logic_vector(7 downto 0); --键盘输入信号
high1 :out std_logic; --高低音节信号
spkout :out std_logic); --音频信号
end top;
architecture Behavioral of top is
component automusic
Port ( clk :in std_logic;
Auto: in std_logic;
index2:in std_logic_vector(7 downto 0);
index0 : out std_logic_vector(7 downto 0));
end component;
component tone
Port ( index : in std_logic_vector(7 downto 0);
code : out std_logic_vector(6 downto 0);
high : out std_logic;
tone0 : out integer range 0 to 2047);
end component;
component speaker
Port ( clk1 : in std_logic;
tone1 : in integer range 0 to 2047;
spks : out std_logic);
end component;
signal tone2: integer range 0 to 2047;
signal indx:std_logic_vector(7 downto 0);
begin
u0:automusic port map(clk=>clk32MHZ,index2=>index1,index0=>indx,Auto=>handtoAuto);
u1: tone port map(index=>indx,tone0=>tone2,code=>code1,high=>high1);
u2: speaker port map(clk1=>clk32MHZ,tone1=>tone2,spks=>spkout);
end Behavioral;
(2)仿真
顶层文件仿真图如图8.18.2所示。