思路:每位互相异或^bus
每位异或后:sel为1,奇校验
奇数个1,check=1;偶数个1,check=0;与 ^bus相同
sel为0,偶校验
奇数个1,check=0;偶数个1,check=1;与 ^bus相反
那么可以直接通过赋值语句assign check=sel?(^bus):(~^bus);就可以实现通过sel选择输出
解法一:
`timescale 1ns/1ns
module odd_sel
(
input [31:0] bus,
input sel,
input check
);
assign check = sel?(^bus):(~^bus);
endmodule
解法二:
`timescale 1ns/1ns
module odd_sel(
input [31:0] bus,
input sel,
output check
);
wire odd;
assign odd = ^bus;
assign check = sel?odd:~odd;
endmodule
解法三:这个代码还是很容易理解的
`timescale 1ns/1ns
module odd_sel
(
input [31:0] bus,
input sel,
input check
);
reg out_temp;
wire odd_even;
assign odd_even = ^ bus;
always@(*)begin
case(sel)
1'b0:
if(odd_even == 0)
out_temp = 1;
else
out_temp = 0;
1'b1:
if(odd_even == 1)
out_temp = 1;
else
out_temp =0;
default: out_temp = 0;
endcase
end
assign check = out_temp;
endmodule
解法四:有点不理解
`timescale 1ns/1ns
module odd_sel(
input [31:0] bus,
input sel,
output check
);
//*************code***********//
wire [32:0] a;
assign a = {sel,bus[31:0]};
assign check = ~(^a);
//*************code***********//
endmodule
其余解法和这些雷同