- Read the offset of "Link Status" reg in config space.
Byte Offset of "Capabilty Pointer" in Type1 Config Space Header is 0x34, the value in 0x34 in config space points to the first entry of a linked lists of Cap Structures. Go to 0x34 and obtained 0x40 which is the offset of the first Cap Structure. First DWORD 0x4801 in the first Cap structure identifies the Cap ID and version and points to the next Capability, 0X48 point to Next Capability Structure, 0x01 indicates Cap ID but it doesn't meet the pre-defined ID(0x10) in spec. So continually go to next Capability Structure 0x48, obtained Cap ID "0x05" which doesn't meet the required ID(0x10) either, so continually go to next Capability Structure 0x68, obtained Cap ID 0x10 which meets the requirement.
0x34 ->0x40->0x4801->0x6805->0xa410(Cap ID 0x10 indicates this is a "PCI Express Capability structure", "Link Status" register is in "PCI Express Capability structure". )
So 0x68 is the offset of "PCI Express Capability structure" for BDF(01:00.0) in config space, 0x12 is offset of "Link Status" register in this Cap Structure. 0x68+0x12=0x7A should be the offset of "Link Status Register" in config space.
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"setpci -s 01:00.0 7A.w ", readout Link Status reg value 0x0105.
The following is configuration space example analyzed by Protocol Analyzer and copied from CSDN.
How to read PCIe Link Status via command (如何读PCIE Link Status)
于 2024-03-18 16:40:21 首次发布