library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port( clk : in std_logic; -- 输入 1mhz 时钟
reset: in std_logic; -- 时钟复位
mod_set : in std_logic_vector(1 downto 0); --模式调节选择 00：显示时间 01：调节时钟 10: 闹钟
minute_set : in std_logic; --分位调节
hout_set : in std_logic; --时位调节
cen : in std_logic; --键入信号
alarm_load : in std_logic;
segment: out std_logic_vector(7 downto 0); --段选信号
status: out std_logic_vector(6 downto 0);
led: out std_logic_vector(23 downto 0)); --位选信号
end clock;
architecture bav of clock is
--调用时钟计数模块声明
component hour_l is
port( h_clear : in std_logic;
h_load : in std_logic;
h_clk : in std_logic;
clock_hour: buffer std_logic_vector(7 downto 0));
end component;
--调用分频模块声明
component erzp is
port( clk_1mhz: in std_logic;
clk_1hz: out std_logic;
clk_5hz: out std_logic;
clk_250hz: out std_logic);
end component;
--调用分钟计数模块声明
component minute_l is
port( m_clear : in std_logic;
m_load : in std_logic;
m_clk : in std_logic;
set_hour : in std_logic;
minute_cout : out std_logic;
clock_minute : buffer std_logic_vector(7 downto 0));
end component;
--调用秒钟计数模块声明
component second_1 is
port( s_en : in std_logic;
s_clear : in std_logic;
s_load : in std_logic;
s_clk : in std_logic;
set_minute: in std_logic;
second_cout : out std_logic;
clock_second: buffer std_logic_vector(7 downto 0));
end component;
--调用数码显示模块声明
component display is
port( scan_clk,rst : in std_logic;
hour,minute,second : in std_logic_vector(7 downto 0);
qh : out std_logic_vector(7 downto 0);
y : out std_logic_vector(6 downto 0));
end component;
--调用时钟调节模块声明
component adjust is
port( en : in std_logic_vector(1 downto 0);
add : in std_logic;
output_shi_h : out std_logic_vector(3 downto 0);
output_shi_l : out std_logic_vector(3 downto 0);
output_fen_h : out std_logic_vector(3 downto 0);
output_fen_l : out std_logic_vector(3 downto 0);
output_miao_h : out std_logic_vector(3 downto 0);
output_miao_l : out std_logic_vector(3 downto 0));
end component;
--调用闹钟模块声明
component alarm is
port ( in_set : in std_logic;
minute_in : in std_logic_vector(7 downto 0);
hour_in : in std_logic_vector(7 downto 0);
alarm_in_h : in std_logic;
alarm_in_m : in std_logic;
out_set : out std_logic;
alarm_load : in std_logic;
minute_out : out std_logic_vector(7 downto 0);
hour_out : out std_logic_vector(7 downto 0));
end component;
--调用消抖模块声明
component key is
port ( clk,kin : in std_logic;
kout : out std_logic);
end component;
--调用模式选择模块声明
component sel is
port ( md : in std_logic_vector(1 downto 0);
in_h:in std_logic_vector(7 downto 0);
in_m:in std_logic_vector(7 downto 0);
in_s:in std_logic_vector(7 downto 0);
alarm_h:in std_logic_vector(7 downto 0);
alarm_m:in std_logic_vector(7 downto 0);
pla_h:out std_logic_vector(7 downto 0);
pla_m:out std_logic_vector(7 downto 0);
pla_s:out std_logic_vector(7 downto 0);
adjust_t:out std_logic;
ala_t:out std_logic);
end component;
--调用led流水灯模块声明
component led_l is
port ( in_set : in std_logic;
clk : in std_logic;
led : buffer std_logic_vector(23 downto 0));
end component;
signal c_co,m_co: std_logic; --秒钟、时钟进位信号
signal in_hour,in_minute,in_second: std_logic_vector(7 downto 0); --秒、时、分数据信号
signal clock_1,clock_2,clock_3: std_logic; --计数时钟、扫描时钟
signal en_minute,en_hour: std_logic;
signal hour_dh, min_dh, sec_dh:std_logic_vector(7 downto 0); --时间数据
signal load:std_logic;
signal ala_h,ala_m:std_logic_vector(7 downto 0); --闹钟数据
signal x:std_logic; --闹钟信号
signal y:std_logic;
begin
u0: erzp port map ( clk_1mhz=>clk,clk_1hz=>clock_1,clk_5hz=>clock_2,clk_250hz=>clock_3);
u1: key port map ( clk=>clock_2,kin=>minute_set,kout=>en_minute);
u2: key port map ( clk=>clock_2,kin=>hout_set,kout=>en_hour);
u3: led_l port map ( in_set=>y,clk=>clock_3,led=>led);
u4: sel port map ( md=>mod_set,in_h=>hour_dh,in_m=>min_dh,in_s=>sec_dh,alarm_h=>ala_h,alarm_m=>ala_m,adjust_t=>load,
pla_h=>in_hour,pla_m=>in_minute,pla_s=>in_second,ala_t=>x);
u5: alarm port map ( minute_in=>min_dh,hour_in=>hour_dh,alarm_in_h=>en_hour,alarm_in_m=>en_minute,in_set=>x,
out_set=>y,minute_out=>ala_m,hour_out=>ala_h,alarm_load=>alarm_load);
u6: second_1 port map ( s_clk=>clock_1,s_clear=>reset,s_load=>load,s_en=>cen,second_cout=>c_co,set_minute=>en_minute,
clock_second=>sec_dh);
u7: minute_l port map ( m_clk=>c_co,m_clear=>reset,m_load=>load,minute_cout=>m_co,set_hour=>en_hour,
clock_minute=>min_dh);
u8: hour_l port map ( h_clk=>m_co,h_clear=>reset,h_load=>load,clock_hour=>hour_dh);
u9: display port map ( scan_clk=>clk,rst=>reset,qh=>segment,y=>status,hour=>in_hour,minute=>in_minute,
second=>in_second);
end bav;
--时钟计数模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour_l is
port( h_clear : in std_logic;
h_load : in std_logic;
h_clk : in std_logic;
clock_hour: buffer std_logic_vector(7 downto 0));
end hour_l;
architecture behave of hour_l is
begin
process (h_clk)
variable tmpl,tmph :std_logic_vector(3 downto 0);
begin
if(h_clear='0') then --异步清零
tmpl:="0000";
tmph:="0000";
else
if(h_clk'event and h_clk='1')then
if (tmpl="1001" or (tmph="0010"and tmpl="0011")) then
tmpl:="0000";
if(tmph="0010" ) then
tmph:="0000";
else
tmph:=tmph+1;
end if;
else
tmpl:=tmpl+1;
end if;
end if;
end if;
clock_hour(3 downto 0) <= tmpl(3 downto 0);
clock_hour(7 downto 4) <= tmph(3 downto 0);
end process;
end behave;
--分钟计数模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minute_l is
port( m_clear : in std_logic; --清零
m_load : in std_logic; --时间调节信号
m_clk : in std_logic; --时钟信号
set_hour : in std_logic; --调节时位
minute_cout : out std_logic; --进位
clock_minute : buffer std_logic_vector(7 downto 0)); --输出信号
end minute_l;
architecture bhv of minute_l is
signal co :std_logic;
begin
process (m_clk)
variable tmpl,tmph :std_logic_vector(3 downto 0);
begin
if (m_clear='0') then
tmpl:="0000";
tmph:="0000";
else
if(m_clk'event and m_clk='1')then
if(tmpl="1001")then
tmpl:="0000";
if(tmph="0101")then
tmph:="0000";
else
tmph:=tmph+1;
end if;
else
tmpl:=tmpl+1;
end if;
end if;
end if;
clock_minute(3 downto 0)<=tmpl;
clock_minute(7 downto 4)<=tmph;
end process;
process
begin
wait until (m_clk='1');
if(clock_minute="01011001")then
co<='1';
else
co<='0';
end if;
end process;
process(m_load)
begin
if(m_load='1')then
minute_cout <= co or (not set_hour);
else
minute_cout <= co;
end if;
end process;
end bhv;
--秒钟计数模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second_1 is
port( s_en : in std_logic;
s_clear : in std_logic;
s_load : in std_logic;
set_minute : in std_logic;
s_clk : in std_logic;
second_cout : out std_logic;
clock_second: buffer std_logic_vector(7 downto 0));
end second_1;
architecture bhv of second_1 is
signal co : std_logic;
begin
process (s_clk)
variable tmpl,tmph :std_logic_vector(3 downto 0);
begin
if (s_clear='0') then
tmpl:="0000";
tmph:="0000";
else
if(s_clk'event and s_clk='1')then
if(s_en='1')then
if(tmpl="1001")then
tmpl:="0000";
if(tmph="0101")then
tmph:="0000";
else
tmph:=tmph+1;
end if;
else
tmpl:=tmpl+1;
end if;
end if;
end if;
end if;
clock_second(3 downto 0)<=tmpl;
clock_second(7 downto 4)<=tmph;
end process;
process
begin
wait until(s_clk='1');
if(clock_second="01011001")then
co<='1';
else
co<='0';
end if;
end process;
process(s_load)
begin
if(s_load='1')then
second_cout <= co or (not set_minute);
else
second_cout <= co;
end if;
end process;
end bhv;
--闹钟模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alarm is
port ( in_set : in std_logic; --闹钟控制信号
minute_in : in std_logic_vector(7 downto 0); --时间信息的输入
hour_in : in std_logic_vector(7 downto 0);
alarm_in_h : in std_logic; --设定闹钟时间
alarm_in_m : in std_logic;
out_set : out std_logic; --输出LED闪烁信号
alarm_load : in std_logic; --闹钟开关信号
minute_out : out std_logic_vector(7 downto 0); --显示设定时间
hour_out : out std_logic_vector(7 downto 0));
end entity;
architecture bhv of alarm is
begin
process(alarm_in_h,alarm_in_m)
variable tmpl_m,tmph_m:std_logic_vector(3 downto 0);
variable tmpl_h,tmph_h:std_logic_vector(3 downto 0);
begin
if(in_set='1')then
if(alarm_in_m'event and alarm_in_m='1')then
if(tmpl_m="1001")then
tmpl_m:="0000";
if(tmph_m="0101")then
tmph_m:="0000";
else
tmph_m:=tmph_m+1;
end if;
else
tmpl_m:=tmpl_m+1;
end if;
end if;
if(alarm_in_h'event and alarm_in_h='1')then
if (tmpl_h="1001" or (tmph_h="0010"and tmpl_h="0011"))then
tmpl_h:="0000";
if(tmph_h="0010" ) then
tmph_h:="0000";
else
tmph_h:=tmph_h+1;
end if;
else
tmpl_h:=tmpl_h+1;
end if;
end if;
hour_out<=tmph_h & tmpl_h;
minute_out<=tmph_m & tmpl_m;
end if;
if(alarm_load='1')then
if((hour_in= tmph_h &tmpl_h)and (minute_in=tmph_m & tmpl_m)) then
out_set<='1';
else
out_set<='0';
end if;
else
out_set<='0';
end if;
end process;
end bhv;
--数码显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port( scan_clk,rst : in std_logic;
hour,minute,second : in std_logic_vector(7 downto 0); --输入时间信息
qh : out std_logic_vector(7 downto 0); -- 位选信号
y : out std_logic_vector(6 downto 0)); --段选信号
end display;
architecture bhv of display is
signal date: std_logic_vector(3 downto 0);
signal place:std_logic_vector(2 downto 0);
begin
process(scan_clk,rst)
variable q:std_logic_vector(2 downto 0);
begin
if rst='0' then q:=(others=>'0');
elsif scan_clk'event and scan_clk='1' then
if(q<7) then
q:=q+1;
else
q:=(others=>'0');
end if;
end if;
case q is
when "000" =>date<=second(3 downto 0);
when "001" =>date<=second(7 downto 4);
when "010" =>date<=minute(3 downto 0);
when "011" =>date<=minute(7 downto 4);
when "100" =>date<=hour(3 downto 0);
when "101" =>date<=hour(7 downto 4);
when others =>date<="1010";
end case;
place<=q;
end process;
process(place)
begin
case date is
when "0000"=>y<="1111110";
when "0001"=>y<="0110000";
when "0010"=>y<="1101101";
when "0011"=>y<="1111001";
when "0100"=>y<="0110011";
when "0101"=>y<="1011011"; --显示译码
when "0110"=>y<="1011111";
when "0111"=>y<="1110000";
when "1000"=>y<="1111111";
when "1001"=>y<="1111011";
when "1010"=>y<="0000001";
when others=>null;
end case;
end process;
with place select
qh<= "11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011", --3-8译码
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
"01111111" when "111",
"11111111" when others;
end bhv;
--分频模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity erzp is
port( clk_1mhz: in std_logic;
clk_1hz: out std_logic;
clk_5hz: out std_logic;
clk_250hz: out std_logic);
end erzp;
architecture one of erzp is
begin
process(clk_1mhz)
variable q1: integer range 0 to 100000;
variable q2: integer range 0 to 200000;
variable q3: integer range 0 to 4000;
begin
if (clk_1mhz'event and clk_1mhz='1')then
-------------------1hz--------------------------
if q1=99999 then
q1:=0;
else
q1:=q1+1;
end if;
if q1<=49999 then
clk_1hz<='1';
else
clk_1hz<='0';
end if;
-------------------5hz--------------------------
if q2=99 then
q2:=0;
else
q2:=q2+1;
end if;
if q2<=49 then
clk_5hz<='1';
else
clk_5hz<='0';
end if;
-------------------250hz--------------------------
if q3=1200 then
q3:=0;
else
q3:=q3+1;
end if;
if q3<=600 then
clk_250hz<='1';
else
clk_250hz<='0';
end if;
end if;
end process ;
end one ;
--led流水灯显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led_l is
port ( in_set : in std_logic;
clk : in std_logic;
led : buffer std_logic_vector(23 downto 0));
end entity;
architecture bhv of led_l is
signal sel:std_logic_vector(4 downto 0); --位选信号 --位
signal xel:std_logic;
begin
process(clk)
variable a :std_logic_vector(4 downto 0);
begin
if(in_set='1')then
if(clk'event and clk='1')then
if(a<23)then --位选计数
a:=a+1;
else
a:=(others=>'0');
end if;
end if;
sel<=a;
else
sel<="11000";
end if;
end process;
process(clk)
variable q :integer range 0 to 2000;
variable a :std_logic;
variable q1:integer range 0 to 20;
begin
if(clk'event and clk='1')then
q:=q+1;
if q<499 then
case sel is
when "00000"=>led<="000000000000000000000001";
when "00001"=>led<="000000000000000000000010";
when "00010"=>led<="000000000000000000000100";
when "00011"=>led<="000000000000000000001000";
when "00100"=>led<="000000000000000000010000";
when "00101"=>led<="000000000000000000100000";
when "00110"=>led<="000000000000000001000000";
when "00111"=>led<="000000000000000010000000";
when "01000"=>led<="000000000000000100000000";
when "01001"=>led<="000000000000001000000000";
when "01010"=>led<="000000000000010000000000";
when "01011"=>led<="000000000000100000000000";
when "01100"=>led<="000000000001000000000000";
when "01101"=>led<="000000000010000000000000";
when "01110"=>led<="000000000100000000000000";
when "01111"=>led<="000000001000000000000000";
when "10000"=>led<="000000010000000000000000";
when "10001"=>led<="000000100000000000000000";
when "10010"=>led<="000001000000000000000000";
when "10011"=>led<="000010000000000000000000";
when "10100"=>led<="000100000000000000000000";
when "10101"=>led<="001000000000000000000000";
when "10110"=>led<="010000000000000000000000";
when "10111"=>led<="100000000000000000000000";
when others =>led<= "000000000000000000000000";
end case;
elsif((q>500)and(q<999))then
case sel is
when "00000"=>led<="100000000000000000000001";
when "00001"=>led<="010000000000000000000010";
when "00010"=>led<="001000000000000000000100";
when "00011"=>led<="000100000000000000001000";
when "00100"=>led<="000010000000000000010000";
when "00101"=>led<="000001000000000000100000";
when "00110"=>led<="000000100000000001000000";
when "00111"=>led<="000000010000000010000000";
when "01000"=>led<="000000001000000100000000";
when "01001"=>led<="000000000100001000000000";
when "01010"=>led<="000000000010010000000000";
when "01011"=>led<="000000000001100000000000";
when "01100"=>led<="000000000001100000000000";
when "01101"=>led<="000000000010010000000000";
when "01110"=>led<="000000000100001000000000";
when "01111"=>led<="000000001000000100000000";
when "10000"=>led<="000000010000000010000000";
when "10001"=>led<="000000100000000001000000";
when "10010"=>led<="000001000000000000100000";
when "10011"=>led<="000010000000000000010000";
when "10100"=>led<="000100000000000000001000";
when "10101"=>led<="001000000000000000000100";
when "10110"=>led<="010000000000000000000010";
when "10111"=>led<="100000000000000000000001";
when others =>led<= "000000000000000000000000";
end case;
elsif((q>1000)and(q<1499))then
case sel is
when "00000"=>led<="100000000000000000000000";
when "00001"=>led<="010000000000000000000000";
when "00010"=>led<="001000000000000000000000";
when "00011"=>led<="000100000000000000000000";
when "00100"=>led<="000010000000000000000000";
when "00101"=>led<="000001000000000000000000";
when "00110"=>led<="000000100000000000000000";
when "00111"=>led<="000000010000000000000000";
when "01000"=>led<="000000001000000000000000";
when "01001"=>led<="000000000100000000000000";
when "01010"=>led<="000000000010000000000000";
when "01011"=>led<="000000000001000000000000";
when "01100"=>led<="000000000000100000000000";
when "01101"=>led<="000000000000010000000000";
when "01110"=>led<="000000000000001000000000";
when "01111"=>led<="000000000000000100000000";
when "10000"=>led<="000000000000000010000000";
when "10001"=>led<="000000000000000001000000";
when "10010"=>led<="000000000000000000100000";
when "10011"=>led<="000000000000000000010000";
when "10100"=>led<="000000000000000000001000";
when "10101"=>led<="000000000000000000000100";
when "10110"=>led<="000000000000000000000010";
when "10111"=>led<="000000000000000000000001";
when others =>led<= "000000000000000000000000";
end case;
else
if(sel="11000")then
led<= "000000000000000000000000";
else
if(clk'event and clk='1')then
if q1=40 then
q1:=0;
else
q1:=q1+1;
end if;
if q1<=20 then
a:='1';
else
a:='0';
end if;
if(a='1')then
led<="111111111111111111111111";
else
led<="000000000000000000000000";
end if;
end if;
end if;
end if;
end if;
end process;
end bhv;
--消抖模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity key is
port(clk,kin:in std_logic; --按键按下时为0
kout:out std_logic:='0');
end entity;
architecture behav of key is
begin
process(clk,kin)
variable count1 :integer range 0 to 100;
begin
if kin='0' then
if rising_edge(clk) then
if count1<100 then
count1:=count1+1;
else
count1:=count1;
end if;
if count1<=99 then
kout<='1';
else
kout<='0';
end if;
end if;
else
count1:=0;
kout<='1';
end if;
end process ;
end behav;
--选择模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sel is
port ( md : in std_logic_vector(1 downto 0); --模式选择信号
in_h:in std_logic_vector(7 downto 0); --时间信息
in_m:in std_logic_vector(7 downto 0);
in_s:in std_logic_vector(7 downto 0);
alarm_h:in std_logic_vector(7 downto 0); --设定的闹钟信息
alarm_m:in std_logic_vector(7 downto 0);
pla_h:out std_logic_vector(7 downto 0);
pla_m:out std_logic_vector(7 downto 0); --显示时间
pla_s:out std_logic_vector(7 downto 0);
adjust_t:out std_logic; --时间调节信号
ala_t:out std_logic); --闹钟调节信号
end entity;
architecture bhv of sel is
begin
process(md)
begin
if(md="00")then
pla_h<=in_h;
pla_m<=in_m; --若为"00"则显示时间
pla_s<=in_s;
adjust_t<='0';
ala_t<='0';
elsif(md="01")then
pla_h<=in_h; --若为"01"则显示时间且可调节时间
pla_m<=in_m;
pla_s<=in_s;
adjust_t<='1';
ala_t<='0';
else
pla_h<=alarm_h;
pla_m<=alarm_m; --若为其他则显示闹钟且可调节闹钟
pla_s<="00000000";
adjust_t<='0';
ala_t<='1';
end if;
end process;
end bhv;
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