ngany的博客

132fsm_onehotGiven the following state machine with 1 input and 2 outputs:Suppose this state machine uses one-hot encoding, wherestate[0]throughstate[9]correspond to the states S0 though S9, respectively. The outputs are zero unless otherwise sp...

128lemmings1The gameLemmingsinvolves critters with fairly simple brains. So simple that we are going to model it using a finite state machine.In the Lemmings' 2D world, Lemmings can be in one of two states: walking left or walking right. It will swi...

三段式状态机 三段式分别指状态跳转逻辑 状态触发器实现 输出逻辑123fsm3combThe following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.Implement only the .

119fsm1This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.This exercise is the same asfsm1s, but using asynchronous reset.Hint...Yes, there are ways to do this ..

116rule90Rule 90is a one-dimensional cellular automaton with interesting properties.The rules are simple. There is a one-dimensional array of cells (on or off). At each time step, the next state of each cell is the XOR of the cell's two current neigh..

113exams/m2014_q4kImplement the following circuit:module top_module ( input clk, input resetn, // synchronous reset input in, output out); reg r1,r2,r3,r4; always@(posedge clk)begin if(!resetn) begin .

107shift4Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.areset: Resets shift register to zero. load: Loads shift register withdata[3:0]instead of shifting. ena: Shift right (q[3]becomes zero,q[...

105countbcdBuild a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three di.