HDLBits练习 123-127 FSM（2）

三段式状态机 三段式分别指

• 状态跳转逻辑
• 状态触发器实现
• 输出逻辑

123 fsm3comb

The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.

Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. 仅实现此状态机的状态转换逻辑和输出逻辑(组合逻辑部分)。Given the current state (state), compute the next_state and output (out) based on the state transition table.

State	Next state		Output
	in=0	in=1
A	A	B	0
B	C	B	0
C	A	D	0
D	C	B	1

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=2'd0, B=2'd1, C=2'd2, D=2'd3;

    // State transition logic: next_state = f(state, in)
    always@* begin
        case(state)
            A:next_state=in?B:A;
            B:next_state=in?B:C;
            C:next_state=in?D:A;
            D:next_state=in?B:C;
        endcase
    end

    // Output logic:  out = f(state) for a Moore state machine
    assign out = (state == D);

endmodule

124 fsm3onehot

The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000.

Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).

State	Next state		Output
	in=0	in=1
A	A	B	0
B	C	B	0
C	A	D	0
D	C	B	1

What does "derive equations by inspection" mean?

One-hot state machine encoding guarantees that exactly one state bit is 1. This means that it is possible to determine whether the state machine is in a particular state by examining only one state bit, not all state bits. This leads to simple logic equations for the state transitions by examining the incoming edges for each state in the state transition diagram.

For example, in the above state machine, how can the state machine can reach state A? It must use one of the two incoming edges: "Currently in state A and in=0" or "Currently in state C and in = 0". Due to the one-hot encoding, the logic equation to test for "currently in state A" is simply the state bit for state A. This leads to the final logic equation for the next state of state bit A: next_state[0] = state[0]&(~in) | state[2]&(~in). The one-hot encoding guarantees that at most one clause (product term) will be "active" at a time, so the clauses can just be ORed together.

When an exercise asks for state transition equations "by inspection", use this particular method. The judge will test with non-one-hot inputs to ensure your logic equations follow this method, rather that doing something else (such as resetting the FSM) for illegal (non-one-hot) combinations of the state bits.

Although knowing this algorithm isn't necessary for RTL-level design (the logic synthesizer handles this), it is illustrative of why one-hot FSMs often have simpler logic (at the expense of more state bit storage), and this topic frequently shows up on exams in digital logic courses.

Hint...

Logic equations for one-hot state transition logic can be derived by looking at in-edges of the state transition diagram.

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = state[0]&(~in) | state[2]&(~in);
    assign next_state[B] = (state[0]|state[1]|state[3])&(in);
    assign next_state[C] = state[1]&(~in) | state[3]&(~in);
    assign next_state[D] = state[2]∈

    // Output logic: 
    assign out = state[D];

endmodule

125 fsm3

See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.

State	Next state		Output
	in=0	in=1
A	A	B	0
B	C	B	0
C	A	D	0
D	C	B	1

Hint...

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
    
    parameter A=2'd0,B=2'd1,C=2'd2,D=2'd3;

    // State transition logic\
    reg [1:0] state_reg,state_next;
    always@* begin
        case(state_reg)
            A:state_next=in?B:A;
            B:state_next=in?B:C;
            C:state_next=in?D:A;
            D:state_next=in?B:C;
        endcase
    end

    // State flip-flops with asynchronous reset
    always@(posedge clk ,posedge areset)begin
        if(areset)begin
            state_reg <= A;
        end
        else begin
            state_reg <= state_next;
        end
    end
    
    // Output logic
    assign out = state_reg == D;

endmodule

126 fsm3s

See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)

State	Next state		Output
	in=0	in=1
A	A	B	0
B	C	B	0
C	A	D	0
D	C	B	1

Hint...

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
    
    parameter A=2'd0,B=2'd1,C=2'd2,D=2'd3;

    // State transition logic\
    reg [1:0] state_reg,state_next;
    always@* begin
        case(state_reg)
            A:state_next=in?B:A;
            B:state_next=in?B:C;
            C:state_next=in?D:A;
            D:state_next=in?B:C;
        endcase
    end

    // State flip-flops with synchronous reset
    always@(posedge clk)begin
        if(reset)begin
            state_reg <= A;
        end
        else begin
            state_reg <= state_next;
        end
    end
    
    // Output logic
    assign out = state_reg == D;

endmodule

127 exams/ece241_2013_q4

Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    
    parameter [1:0] s0=0,s1=1,s2=2,s3=3;
    reg [1:0] state,state_next;
    reg [1:0] fr1_reg,fr2_reg,fr3_reg;
    // State transition logic
    always@* begin
        case(state)
            s0:state_next={1'd0,s[1]};
            s1:state_next={((s[1])&(s[2])),((~s[2])&(s[1]))};
            s2:state_next={((~s[3])&( s[2])&(s[1]))|((s[3])&(s[2])&(s[1])),
                           ((~s[3])&(~s[2])&(s[1]))|((s[3])&(s[2])&(s[1]))};
            s3:state_next={1'd1,s[3]};
        endcase
    end
    
    // State flip-flops with synchronous reset
    always@(posedge clk)begin
        if(reset)begin
            state<=s0;
        end
        else begin
            state <= state_next;
        end
    end
    
    // Output logic
    assign fr1 = ~((state[1])&(state[0]));
    assign fr2 = (~state[1]);
    assign fr3 = ((~state[1])&(~state[0]));
    
    always@(posedge clk)begin
        fr1_reg<=fr1;
        fr2_reg<=fr2;
        fr3_reg<=fr3;
    end
    
    always@* begin
        if((fr1&(~fr1_reg)) | (fr2&(~fr2_reg)) | (fr3&(~fr3_reg)))begin
            dfr<=1'd1;
        end
        else if((~fr1&(fr1_reg)) | (~fr2&(fr2_reg)) | (~fr3&(fr3_reg)))begin
            dfr<=1'd0;
        end
    end


endmodule