HDLBits练习 113-115 Shift Registers

113 exams/m2014_q4k

Implement the following circuit:

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    
    reg r1,r2,r3,r4;

    always@(posedge clk)begin
        if(!resetn) begin
            r1 <= 1'd0;
            r2 <= 1'd0;
            r3 <= 1'd0;
            r4 <= 1'd0;
        end
        else begin
            r4<=r3;
            r3<=r2;
            r2<=r1;
            r1<=in;
        end
    end
    
    assign out = r4;
    
endmodule

114 exams/2014_q4b

Consider the n-bit shift register circuit shown below:

Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.

• Connect the R inputs to the SW switches,
• clk to KEY[0],
• E to KEY[1],
• L to KEY[2], and
• w to KEY[3].
• Connect the outputs to the red lights LEDR[3:0].

(Reuse your MUXDFF from exams/2014_q4a.)

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //
    MUXDFF u0(
        .clk(KEY[0]),
        .e(KEY[1]),
        .l(KEY[2]),
        .w(LEDR[1]),
        .r(SW[0]),
        .q(LEDR[0])
    );
    MUXDFF u1(
        .clk(KEY[0]),
        .e(KEY[1]),
        .l(KEY[2]),
        .w(LEDR[2]),
        .r(SW[1]),
        .q(LEDR[1])
    );
	MUXDFF u2(
        .clk(KEY[0]),
        .e(KEY[1]),
        .l(KEY[2]),
        .w(LEDR[3]),
        .r(SW[2]),
        .q(LEDR[2])
    );
    MUXDFF u3(
        .clk(KEY[0]),
        .e(KEY[1]),
        .l(KEY[2]),
        .w(KEY[3]),
        .r(SW[3]),
        .q(LEDR[3])
    );
    
endmodule

module MUXDFF (
    input clk,
    input e,
    input l,
    input w,
    input r,
    output q
);
    always@(posedge clk)begin
        if(l)begin
            q<=r;
        end
        else if(e)begin
            q<=w;
        end
        else begin
            q<=q;
        end
    end
    
endmodule

115 exams/ece241_2013_q12

In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function.

First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    
    reg[7:0]shift_reg;
    always@(posedge clk)begin
        if(enable) begin
            shift_reg<={shift_reg[6:0],S};
        end
    end
    
    always@* begin
        case({A,B,C})
            3'd0:Z=shift_reg[0];
            3'd1:Z=shift_reg[1];
            3'd2:Z=shift_reg[2];
            3'd3:Z=shift_reg[3];
            3'd4:Z=shift_reg[4];
            3'd5:Z=shift_reg[5];
            3'd6:Z=shift_reg[6];
            3'd7:Z=shift_reg[7];
        endcase
    end

endmodule