FPGA四位频率计设计Verilog语言实现

设计任务:

                   用混合设计的方法设计一个4位频率计,主要设计模块为测频控制器、计数器、锁存器、译码器,显示器为7段LED显示管。并合理选择实验模式,进行下载测试。

 

 

//计数器模块

modulejishu(clk,zamen,fuwei,jieguo1,jieguo2,jieguo3,jieguo4);

         inputclk;

         inputzamen;

         inputfuwei;

         output[3:0]jieguo1,jieguo2,jieguo3,jieguo4;

         reg[3:0]jieguo1,jieguo2,jieguo3,jieguo4;

        

         always @(posedgeclk)

                   if(fuwei)

                   begin

                   jieguo1<=4'b0000;

                   jieguo2<=4'b0000;

                   jieguo3<=4'b0000;

                   jieguo4<=4'b0000;

                   end

                   else if(zamen)     //4个if完成4位计数器的进位

                   begin

                            if(jieguo1==4'b1001)

                                     begin jieguo1<=4'b0000;jieguo2<=jieguo2+1;

                                               if(jieguo2==4'b1001)

                                                        begin jieguo2<=4'b0000;jieguo3<=jieguo3+1;

                                                                 if(jieguo3==4'b1001)

                                                                           begin jieguo3<=4'b0000;jieguo4<=jieguo4+1;

                                                                                    if(jieguo4==4'b1001)

                                                                                              jieguo4<=4'b0000;

                                                                           end

                                                        end

                                     end

                            else

                                     jieguo1<=jieguo1+1;

                   end

endmodule      

                  

 

 

//译码器模块

module DECL7S(A,LED7S);

input[3:0]A;

output[6:0]LED7S;

reg[6:0]LED7S;

 

always@(A)

begin

case(A)

    4'b0000: LED7S<=7'b0111111;

    4'b0001: LED7S<=7'b0000110;

    4'b0010: LED7S<=7'b1011011;

    4'b0011: LED7S<=7'b1001111;

    4'b0100: LED7S<=7'b1100110;

    4'b0101: LED7S<=7'b1101101;

    4'b0110: LED7S<=7'b1111101;

    4'b0111: LED7S<=7'b0000111;

    4'b1000: LED7S<=7'b1111111;

    4'b1001: LED7S<=7'b1101111;

    4'b1010: LED7S<=7'b1110111;

    4'b1011: LED7S<=7'b1111100;

    4'b1100: LED7S<=7'b0111001;

    4'b1101: LED7S<=7'b1011110;

    4'b1110: LED7S<=7'b1111001;

    4'b1111: LED7S<=7'b1110001;

default:LED7S<=7'b0111111;

endcase

end

endmodule

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

//测频模块

modulecepin(CLKK,CNT_EN,RST_CNT,LOAD);

         input CLKK;

         output CNT_EN,RST_CNT,LOAD;

         wire CNT_EN,LOAD;

         reg RST_CNT,JICUN;

         always @(posedge CLKK)//两个always语句块实现测频功能

                   JICUN<=~JICUN;

         always @(CLKK or JICUN)

         begin

         if(CLKK==1'b0 & JICUN==1'b0) RST_CNT<=1'b1;

         else RST_CNT<=1'b0;

         end

         assign LOAD=~JICUN;

         assign CNT_EN=JICUN;

endmodule

 

 

 

//锁存器

module suocun(result1,result2,result3,result4,data1,data2,data3,data4,kaiguan);

         output[3:0]data1,data2,data3,data4;

         input[3:0]result1,result2,result3,result4;

         inputkaiguan;

         reg[3:0]data1,data2,data3,data4;

         always @(posedgekaiguan)

         if(kaiguan)

         begin

                   data1<=result1;

                   data2<=result2;

                   data3<=result3;

                   data4<=result4;

         end

endmodule

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