本文摘自《Advanced FPGA Design》一书，介绍了FPGA设计的优化策略，包括速度优化（如通过循环展开提高吞吐量）、面积优化（如通过资源共享减少重复逻辑）和低功耗优化（如使用时钟控制资源降低动态功耗）。优化过程中需权衡速度、面积和功耗的关系，避免潜在的设计问题。
Advanced FPGA Design: Architecture, Implementation, and Optimization是一本好书
基本上所有能包含的情况都有所描述，属于手册型的，适合边学边看
以下摘录了前几章的基本架构优化思路
cipher个人感觉这里面有些种种因素相互制衡的味道比较重，比如追求速度就得损失面积，
一味的缩小面积速度肯定会下降，功耗肯定是和面积挂钩的，完美设计基本上是不可能了
速度优化的关键点：
A high-throughtput architecture is one that maximizes the number of bits per
second that can be processed by a design.
Unrolling an iterative loop increases throughput.
The penalty for unrolling an iterative loop is a proportional increase in area.
A low-latency architecture is one that minimizes the delay from input of a
module to the output.
Latency can be reduced by removing pipeline registers.
The penalty for removing pipeline registers is an increase in combinatorial
delay between registers.
Timing refers to the clock speed of a design. A design meets timing when the
maximum delay between
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