UART验证项目之测试激励
一、寄存器的读写权限以及复位权限检查
uvm中提供了两个seq用于完成这个测试,可以直接调用,他的原理是比较testbench中的寄存器模型的默认值和dut中写的默认值是否一致
class reg_vseq extends base_vseq;
`uvm_object_utils(reg_vseq)
//uvm中自带的sequence
uvm_reg_hw_reset_seq rst_seq;//寄存器复位检查
uvm_reg_bit_bash_seq bitbash_seq;//寄存器读写权限检查
function new(string name="reg_vseq");
super.new(name);
endfunction
virtual task body();
#10us;
//例化后把我们的寄存器模型变量赋值给seq中自带的model变量即可
rst_seq =new("rst_seq");
rst_seq.model = p_sequencer.p_rm;
rst_seq.start(null);
bitbash_seq = new("bitbash_seq");
bitbash_seq.model = p_sequencer.p_rm;
bitbash_seq.start(null);
endtask
endclass
class tc_uart_reg extends tc_base;
`uvm_component_utils(tc_uart_reg)
function new(string name="tc_uart_reg",uvm_component parent);
super.new(name,parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
//这里采用default_sequence的方式启动sequence,和下面run_phase中的start二选一,实际上对于一些简单的激励,可以用default_sequence来发送,但应该尽量摒弃这种方式
uvm_config_db#(uvm_object_wrapper)::set(this,"v_sqr.main_phase","default_sequence",reg_vseq::type_id::get());
//跳过以下四个寄存器的检查(可选)
uvm_resource_db#(bit)::set({
"REG::",rm.get_full_name(), ".UARTDR"}, "NO_REG_TESTS", 1, this);
uvm_resource_db#(bit)::set({
"REG::",rm.get_full_name(), ".UARTRSR"}