always @(posedge clk or negedge rst_n)
if(rf1_ren == 1'b1 & rst_n) begin
if (rf1_data_out != rf1_data_out_m) begin
$error("read is not match") ;
end
end
解决办法, 判决条件中加入 “& rst_n”
always @(posedge clk or negedge rst_n)
if(rf1_ren == 1'b1 & rst_n) begin
if (rf1_data_out != rf1_data_out_m) begin
$error("read is not match") ;
end
end
解决办法, 判决条件中加入 “& rst_n”