Verilog 扫描数码管 5461BS 实验代码

编码速度明显提上去了，不到1个小时，竟然用Verilog HDL写了个数码管扫描的模块。实验十分顺利！

系统使用EP2C5T144C8 CycloneII FPGA，时钟为50MHz有源晶振。扫描频率为秒级，肉眼可观察，现象十分明显。

 

module led7seg(
	input i_clk,
	input i_rstn,
	output [7:0]o_data,
	output [3:0]o_com
);

reg [22:0] r_cnt ;
always @(posedge i_clk) begin
	if(!i_rstn)
		r_cnt <= 0;
	else
		r_cnt <= r_cnt + 23'd1;
end

reg [3:0]r_num;
reg [1:0] r_num2;
always @(posedge i_clk) begin
	if(!i_rstn) begin
		r_num <= 0;
	end else if(r_cnt == 23'd128) begin
		if(r_num<9)
			r_num <= r_num + 4'b1;
		else
			r_num <= 0 ;
		r_num2 <= r_num2 + 2'b1;
	end
end

reg [7:0] r_data;
always @(posedge i_clk) begin
	if(!i_rstn)
		r_data<= 8'b0;
	else
		casex(r_num)
			0:r_data<=8'hc0;
			1:r_data<=8'hf9;
			2:r_data<=8'ha4;
			3:r_data<=8'hb0;
			4:r_data<=8'h99;
			5:r_data<=8'h92;
			6:r_data<=8'h82;
			7:r_data<=8'hf8;
			8:r_data<=8'h80;
			9:r_data<=8'h90;
			default:
			  r_data<= 8'hff;
			
		endcase
end

reg [3:0] r_com ;
always @(posedge i_clk) begin
	if(!i_rstn) begin
		r_com<= 0;
	end else begin
		r_com <= 4'b1 << r_num2 ;
	end
end

assign o_data = r_data ;
assign o_com = r_com ;
endmodule