mips cpu 产生exception/interrupt后,cpu 会跳到特定的几个地址上,
BEV=0时,一般的在0x80000180,当然还有些其他地址,详细的要去看mips书籍
这里有这样的代码
FUNC_START(other_vector)
mfc0 k0,cause # K0 = exception cause
nop
andi k0,k0,0x7F # isolate exception code
la k1,hal_vsr_table # address of VSR table
add k1,k1,k0 # offset of VSR entry
lw k1,0(k1) # k1 = pointer to VSR
jr k1 # go there
nop # (delay slot)
FUNC_END(other_vector)
从cause 里取出exception ExcCode,然后到hal_vsr_table 取相应的处理vsr,
hal_vsr_table的内容是由 hal_mon_init 填充的
.macro hal_mon_init
la a0,__default_interrupt_vsr
la a1,__default_exception_vsr
la a3,hal_vsr_table
sw a0,0(a3)
sw a1,1*4(a3)
sw a1,2*4(a3)
sw a1,3*4(a3)
sw a1,4*4(a3)
sw a1,5*4(a3)
sw a1,6*4(a3)
sw a1,7*4(a3)
sw a1,8*4(a3)
sw a1,9*4(a3)
sw a1,10*4(a3)
sw a1,11*4(a3)
sw a1,12*4(a3)
sw a1,13*4(a3)
sw a1,14*4(a3)
sw a1,15*4(a3)
sw a1,32*4(a3)
sw a1,33*4(a3)
sw a1,34*4(a3)
.endm
这里填充的是__default_interrupt_vsr和__default_exception_vsr,
ExcCode=0是interrupt,其他的都是exception,就是说产生interrupt会调用
__default_interrupt_vsr,产生exception会调用__default_exception_vsr。
下面的就是这两段代码
##-----------------------------------------------------------------------------
## Default exception VSR.
## Saves machine state and calls external handling code.
FUNC_START(__default_exception_vsr)
# We enter here with all of the CPU state still
# in its registers except:
# K0 = vector index
# K1 = address of this function
move k1,sp # K1 = original SP
>>保存现场到堆栈
addi sp,sp,-mips_exception_decrement
# space for registers + safety margin
sw k0,mipsreg_vector(sp) # store vector
# store GPRs
.set noat
sgpr 0,sp
sgpr 1,sp
sgpr 2,sp
sgpr 3,sp
sgpr 4,sp
sgpr 5,sp
sgpr 6,sp
sgpr 7,sp
sgpr 8,sp
sgpr 9,sp
sgpr 10,sp
sgpr 11,sp
sgpr 12,sp
sgpr 13,sp
sgpr 14,sp
sgpr 15,sp
sgpr 16,sp
sgpr 17,sp
sgpr 18,sp
sgpr 19,sp
sgpr 20,sp
sgpr 21,sp
sgpr 22,sp
sgpr 23,sp
sgpr 24,sp
sgpr 25,sp
# sgpr 26,sp # == K0
# sgpr 27,sp # == K1
sgpr 28,sp # == GP
# sgpr 29,sp # == SP
sgpr 30,sp # == FP
sgpr 31,sp # == RA
.set at
mfhi a0
mflo a1
shi a0,sp
slo a1,sp
# K1 contains original SP
ssp k1,sp # store in reg dump
# save remaining machine state registers
mfc0 t0,cause
mfc0
BEV=0时,一般的在0x80000180,当然还有些其他地址,详细的要去看mips书籍
这里有这样的代码
FUNC_START(other_vector)
mfc0 k0,cause # K0 = exception cause
nop
andi k0,k0,0x7F # isolate exception code
la k1,hal_vsr_table # address of VSR table
add k1,k1,k0 # offset of VSR entry
lw k1,0(k1) # k1 = pointer to VSR
jr k1 # go there
nop # (delay slot)
FUNC_END(other_vector)
从cause 里取出exception ExcCode,然后到hal_vsr_table 取相应的处理vsr,
hal_vsr_table的内容是由 hal_mon_init 填充的
.macro hal_mon_init
la a0,__default_interrupt_vsr
la a1,__default_exception_vsr
la a3,hal_vsr_table
sw a0,0(a3)
sw a1,1*4(a3)
sw a1,2*4(a3)
sw a1,3*4(a3)
sw a1,4*4(a3)
sw a1,5*4(a3)
sw a1,6*4(a3)
sw a1,7*4(a3)
sw a1,8*4(a3)
sw a1,9*4(a3)
sw a1,10*4(a3)
sw a1,11*4(a3)
sw a1,12*4(a3)
sw a1,13*4(a3)
sw a1,14*4(a3)
sw a1,15*4(a3)
sw a1,32*4(a3)
sw a1,33*4(a3)
sw a1,34*4(a3)
.endm
这里填充的是__default_interrupt_vsr和__default_exception_vsr,
ExcCode=0是interrupt,其他的都是exception,就是说产生interrupt会调用
__default_interrupt_vsr,产生exception会调用__default_exception_vsr。
下面的就是这两段代码
##-----------------------------------------------------------------------------
## Default exception VSR.
## Saves machine state and calls external handling code.
FUNC_START(__default_exception_vsr)
# We enter here with all of the CPU state still
# in its registers except:
# K0 = vector index
# K1 = address of this function
move k1,sp # K1 = original SP
>>保存现场到堆栈
addi sp,sp,-mips_exception_decrement
# space for registers + safety margin
sw k0,mipsreg_vector(sp) # store vector
# store GPRs
.set noat
sgpr 0,sp
sgpr 1,sp
sgpr 2,sp
sgpr 3,sp
sgpr 4,sp
sgpr 5,sp
sgpr 6,sp
sgpr 7,sp
sgpr 8,sp
sgpr 9,sp
sgpr 10,sp
sgpr 11,sp
sgpr 12,sp
sgpr 13,sp
sgpr 14,sp
sgpr 15,sp
sgpr 16,sp
sgpr 17,sp
sgpr 18,sp
sgpr 19,sp
sgpr 20,sp
sgpr 21,sp
sgpr 22,sp
sgpr 23,sp
sgpr 24,sp
sgpr 25,sp
# sgpr 26,sp # == K0
# sgpr 27,sp # == K1
sgpr 28,sp # == GP
# sgpr 29,sp # == SP
sgpr 30,sp # == FP
sgpr 31,sp # == RA
.set at
mfhi a0
mflo a1
shi a0,sp
slo a1,sp
# K1 contains original SP
ssp k1,sp # store in reg dump
# save remaining machine state registers
mfc0 t0,cause
mfc0