3-8线译码器真值表:
Implementation part:
module Decoder38(data_in,data_out,enable);
input [2:0] data_in;
input enable;
output [7:0] data_out;
reg [7:0] data_out;
always @(data_in)
begin
if (enable == 1)
case(data_in)
3'b000: data_out = 8'b00000001;
3'b001: data_out = 8'b00000010;
3'b010: data_out = 8'b00000100;
3'b011: data_out = 8'b00001000;
3'b100: data_out = 8'b00010000;
3'b101: data_out = 8'b00100000;
3'b110: data_out = 8'b01000000;
3'b111: data_out = 8'b10000000;
default: data_out = 8'bxxxxxxxx;
endcase
else
data_out = 8'b11111111;
end
endmodule
Simulation part:
module Decoder38Test2;
// Inputs
reg [2:0] data_in;
reg enable;
// Outputs
wire [7:0] data_out;
// Instantiate the Unit Under Test (UUT)
Decoder38 uut (
.data_in(data_in),
.data_out(data_out),
.enable(enable)
);
initial begin
// Initialize Inputs
data_in = 0;
enable = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
data_in <= 3'b000;
#100;
data_in <= 3'b001;
#100;
data_in <= 3'b010;
#100;
data_in <= 3'b011;
#100;
data_in <= 3'b100;
#100;
data_in <= 3'b101;
#100;
data_in <= 3'b110;
#100;
data_in <= 3'b111;
end
endmodule
Simulation Behavioral Model:
RTL Schematic: