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原创 verilog modelsim memory 仿真笔记1

ram_tb.v`timescale 1ns/1nsmodule ram_tb();reg clk;reg [7:0] addr;wire [7:0] data;ram ram1( .clk(clk), .addr(addr), .data(data));initialbegin clk = 0; addr = 8'b00000000;en...