VHDL configuration使用

1. congfiguration 功能

        a. 用来指定例化组件使用的实体；

        b. 用来指定例化组件使用的结构体；

2. configuration 语法

        configuration 配置名 of 实体名 is
                for 结构体名
                        for 实例化名:实体名

                                use entity work.实体名(结构体名);
                        end for;

                        for 实例化名:实体名

                                use entity work.实体名(结构体名);
                        end for;

                        ...

                end for
        end configuration 配置名

  note: a. 实例化名可以用all或者others代替；

           b.  每个实例化组件只能被配置一次；

           c. 如果缺省配置，实体使用与组件名字相同的实体，结构体则使用实体中最后一个结构体；

           d. 可以将顶层的配置写进一个单独的文件，每个配置名都可以当作实体进行例化。

3. configuration 用法示例

        top.vhd:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;

entity top is 
	port(
	clk     : in std_logic;
	rst     : in std_logic;
	count   : buffer unsigned(3 downto 0);
	cnt     : buffer unsigned(3 downto 0)
	);

end top;

architecture str of top is

component my_configuration is
	port(
	clk    : in std_logic;
	rst    : in std_logic;
	count  : buffer unsigned(3 downto 0)
	);
end component my_configuration;

component my_test is
	port(
	clock    : in std_logic;
	reset    : in std_logic;
	cnt      : buffer std_logic_vector(3 downto 0)
	);
end component my_test;


begin


	my_configuration_inst: my_configuration
	--my_configuration_inst: configuration work.test1_cfg
	port map(
		clk    => clk,
		rst    => rst,
		count  => count
		);

	my_test_inst: my_configuration  --could replaced by my_test entity, see top1_cfg
	port map(
		clk    => clk,
		rst    => rst,
		count  => cnt
		);

	my_test_inst2: my_test  
	port map(
		clock    => clk,
		reset    => rst,
		cnt      => open
		);

end architecture str;

        my_configuration.vhd 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;

entity my_configuration is 
	port(
	clk     : in std_logic;
	rst     : in std_logic;
	count   : buffer unsigned(3 downto 0)
	);



end my_configuration;


architecture test1 of my_configuration is 
begin
	process (clk) is
	begin
		if rising_edge (clk) then
			count <= count + 1;
		end if;

		if rst = '1' then
			count <= "0000";
		end if;

	end process;


end architecture test1;

architecture test2 of my_configuration is 
begin
	process (clk) is
	begin
		if rising_edge (clk) then
			count <= count + 2;
		end if;

		if rst = '1' then
			count <= "0000";
		end if;

	end process;


end architecture test2;

architecture test3 of my_configuration is 
begin
	process (clk) is
	begin
		if rising_edge (clk) then
			count <= count + 2;
		end if;

		if rst = '1' then
			count <= "0000";
		end if;

	end process;


end architecture test3;



architecture shell of my_configuration is 
begin


end architecture shell;

CONFIGURATION test1_cfg OF my_configuration IS
    FOR test1

    END FOR;
END CONFIGURATION test1_cfg;

CONFIGURATION test2_cfg OF my_configuration IS
    FOR test2

    END FOR;
END CONFIGURATION test2_cfg;

CONFIGURATION shell_cfg OF my_configuration IS
    FOR shell

    END FOR;
END CONFIGURATION shell_cfg;

        my_test.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;

entity my_test is 
	port(
	clock     : in std_logic;
	reset     : in std_logic;
	cnt       : buffer std_logic_vector(3 downto 0)
	);



end my_test;


architecture str of my_test is 
begin
	process (clock) is
	begin
		if rising_edge (clock) then
			cnt <= std_logic_vector(unsigned(cnt) + 1);
		end if;

		if reset = '1' then
			cnt <= "0000";
		end if;

	end process;


end architecture str;

        top_cfg.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;


CONFIGURATION top_cfg OF top IS
    FOR str

    END FOR;
END CONFIGURATION top_cfg;

CONFIGURATION top1_cfg OF top IS
    FOR str
		for my_configuration_inst: my_configuration
			use entity work.my_configuration(test1);
		end for;
        
		for my_test_inst:my_configuration
			use entity work.my_test(str)
				port map(clock => clk,
						 reset => rst,
			   unsigned(cnt)   => count
						);
		end for;

		for all: my_test
			use entity work.my_test(str);
		end for;

    END FOR;
END CONFIGURATION top1_cfg;

CONFIGURATION top2_cfg OF top IS
    FOR str
		for all: my_configuration
			use entity work.my_configuration(test2);
		end for;

		for all: my_test
			use entity work.my_test(str);
		end for;

    END FOR;
END CONFIGURATION top2_cfg;


CONFIGURATION top_shell_cfg OF top IS
    FOR str
		for all: my_configuration
			use entity work.my_configuration(shell);
		end for;

		for all: my_test
			use entity work.my_test(str);
		end for;

    END FOR;
END CONFIGURATION top_shell_cfg;

CONFIGURATION top3_cfg OF top IS
    FOR str
		for all: my_configuration
			use entity work.my_configuration(test3);
		end for;

		for all: my_test
			use entity work.my_test(str);
		end for;

    END FOR;
END CONFIGURATION top3_cfg;