Perl提取Verilog文件内input output信号名，生成信号例化和调用到output.txt文件

 extract_signals.pl

#! /usr/bin/perl -w
use 5.010;
use strict;

my $source_file;
my @source_file_lines;
my $source_signal_name;

my $axis_exchange;

$source_file = "$ARGV[0]";

open SOURCE_FILE,"<",$source_file or die "$!";
open OUTPUT_FILE,">","output.txt";

@source_file_lines = <SOURCE_FILE>;

foreach(@source_file_lines){
    chomp;
    if(/\A\s*input\s+(wire\s+)?\s*(\[\S+.*\:\d+\])?\s*([\w|\d]+)\s*(\,)?/){
#       say OUTPUT_FILE 'wire ' . $2 . ' ' . $3 . ';';
        print OUTPUT_FILE 'wire    ';
        printf OUTPUT_FILE "%-52s",$2;
        print OUTPUT_FILE "\t\t";
        printf OUTPUT_FILE "%-52s",$3;
        print OUTPUT_FILE ';' . "\n";
    }
    elsif(/\A\s*output\s+(wire\s+|reg\s+)?\s*(\[\S+.*\:\d+\])?\s*([\w|\d]+)\s*(\,)?/){
#       say OUTPUT_FILE 'wire ' . $2 . ' ' . $3 . ';';
        print OUTPUT_FILE 'wire    ';
        printf OUTPUT_FILE "%-52s",$2;
        print OUTPUT_FILE "\t\t";
        printf OUTPUT_FILE "%-52s",$3;
        print OUTPUT_FILE ';' . "\n";
    }

}

foreach(@source_file_lines){
    chomp;
    if(/\A\s*input\s+(wire\s+)?\s*(\[\S+.*\:\d+\])?\s*([\w|\d]+)\s*(\,)?/){
#        print OUTPUT_FILE "\t" . '.' . $3 . "\t\t" . '    ( ' . $3 . '     )' . $4;
        print OUTPUT_FILE "\t" . '.';
        printf OUTPUT_FILE "%-51s",$3;
        print OUTPUT_FILE "\t\t" . '( ';
        printf OUTPUT_FILE "%-54s",$3;
        print OUTPUT_FILE "\t" . ')' . $4 . "\n";     
    }
    elsif(/\A\s*output\s+(wire\s+|reg\s+)?\s*(\[\S+.*\:\d+\])?\s*([\w|\d]+)\s*(\,)?/){
#        say OUTPUT_FILE "\t" . '.' . $3 . "\t\t" . '    ( ' . $3 . '     )' . $4; 
        print OUTPUT_FILE "\t" . '.';
        printf OUTPUT_FILE "%-51s",$3;
        print OUTPUT_FILE "\t\t" . '( ';
        printf OUTPUT_FILE "%-54s",$3;
        print OUTPUT_FILE "\t" . ')' . $4 . "\n";    
    }

}

close SOURCE_FILE;
close OUTPUT_FILE;

提取Verilog文件内input output信号名，生成信号例化和调用到output.txt文件
./extract_signals.pl 文件名
eg:./extract_signals.pl a.v