DC综合的脚本总结

#step 1Read&elaborate the RTL file list & check
#==========================================================
set TOP_MODULE spi
analyze -format verilog  [list spi.v serial_parallel.v switch.v]
elaborate $TOP_MODULE  -architecture verilog
current_design $TOP_MODULE
if {
   [Link] == 0} {
   
     echo Link with error!;
      exit;
}
if {
   [check_design] == 0} {
   
     echo check design with error! ;
      exit;
}
#step 2 reset the design first
#===========================================================
reset_design 
#===========================================================
#step 3 write the unmapped ddc file 
#===========================================================
uniquify
set uniquify_naming_style %s_%d
set UNMAPPED_PATH  .unmapped
write -f ddc -hierarchy -output ${
   UNMAPPED_PATH}${
   TOP_MODULE}.ddc
#===========================================================
#step 4Defined clock
#========================