DC综合脚本

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已于 2024-03-28 16:09:34 修改

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分类专栏： IC设计文章标签： windows 服务器芯片

于 2024-03-28 15:33:35 首次发布

本文链接：https://blog.csdn.net/weixin_38368252/article/details/137101959

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本文详细描述了使用SynopsysDC工具进行环境设置、库路径定义、设计编译步骤，包括RTL文件分析、时序检查、约束设置和报告生成等关键过程。

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环境设置

默认脚本 .synopsys_dc.setup
设置环境变量

set SYN_ROOT_PATH 	/home/my_home/work/syn
set RTL_PATH       	$SYN_ROOT_PATH/src
set CONFIG_PATH		$SYN_ROOT_PATH/config
set OUTPUT_PATH 	$SYN_ROOT_PATH/mapped
set SCRIPT_PATH 	$SYN_ROOT_PATH/script
set REPORT_PATH 	$SYN_ROOT_PATH/report
set UNMAPPED_PATH 	$SYN_ROOT_PATH/unmapped

#define work directory
set WORK_PATH 	$SYN_ROOT_PATH/work
set DC_PATH 	$DC_HOME
define_design_lib work -path $WORK_PATH

set BC_LIB_PATH 	std_best_corner/1.8v
set WC_LIB_PATH  	std_worst_corner/1.62v
set IP_BC_LIB_PATH  ip_best/1.8v
set IP_WC_LIB_PATH 	ip_worst/1.62v
set_app_var search_path [list . $search_path 	\
								$BC_LIB_PATH	\
								$WC_LIB_PATH	\
								$IP_BC_LIB_PATH	\
								$IP_WC_LIB_PATH	\
								$RTL_PATH		\
								$SCRIPT_PATH	\
								${DC_PATH}/libraries/syn]

#DC is setup to use this library by default
set_app_var synthetic_library 	[list dw_foundation.sldb standard.sldb]
set_app_var target_library 		[list 	std_best_corner_ccs.db	\
										std_worst_corner_ccs.db	\
										ip_best.db	\
										ip_worst.db]
#Specify for cell resolution during link
set_app_var link_library	"* ${target_library} "
set_app_var symbol_library	[list * ${target_library"]

echo "*************************************************************"
echo "************ End of load .synopsys_dc.setup ************"
echo "*************************************************************"

dc脚本设置

## Prepare
#Intraassignment delays for nonblocking assignment are ignored。（VER-130）
suppress_message VER-130


## SVF
set TOP_DESIGN dig_top
#Generate SVF for LEC
set_svf  [format "%s%s%s"  $OUTPUT_PATH $TOP_DESIGN ".svf"]

## Step 1: Read elaborate the RTL file list & check
analyze -format verilog [list ./src/define.v]
elaborate 		$TOP_DESIGN	-architecture verilog
current_design	$TOP_DESIGN

if {[link] == 0} {
	echo "link with error !"
	exit;
}

if {[check_design] == 0} {
	echo "Check design with error !";
	exit;
}

## Step 2: Reset the design first
reset_design

## Step 3: Write the unmapped ddc file
uniquify
set uniquify_naming_style	"%s_%d"
write -f ddc -hier -output	${UNMAPPED_PATH}/${TOP_DESIGN}.ddc

## Step 4: Define clock
set	CLK_I_NAME			clk
set	CLK_I_PERIOD		10
set	CLK_I_SKEW			[expr ${CLK_PERIOD} * 0.05]
set	CLK_I_TRAN			[expr ${CLK_PERIOD} * 0.01]
set	CLK_I_SRC_LATENCY	[expr ${CLK_PERIOD} * 0.1 ]
set CLK_I_LATENCY		[expr ${CLK_PERIOD} * 0.1 ]

create_clock			-period	$CLK_I_PERIOD	[get_ports $CLK_I_NAME]
set_ideal_network								[get_ports $CLK_I_NAME]
set_dont_touch_network							[get_ports $CLK_I_NAME]
set_drive	0									[get_ports $CLK_I_NAME]
set_clock_uncertainty	-setup	$CLK_I_SKEW		[get_ports $CLK_I_NAME]
set_clock_transition	-max	$CLK_I_TRAN		[get_ports $CLK_I_NAME]
set_clock_latency	-source -max $CLK_I_SRC_LATENCY [get_ports $CLK_I_NAME]
set_clock_latency		-max	$CLK_I_LATENCY	[get_ports $CLK_I_NAME]

## Step 5: Define reset
set			RST_NAME	rst_n
set_ideal_network		[get_ports	$RST_NAME]
set_dont_touch_network	[get_ports	$RST_NAME]
set_drive	0			[get_ports	$RST_NAME]

## Step 6: Set input delay (Using timing budget)
## Assume a weak cell to drive the input pins
set	MAX_LIB_NAME	std_ff_ccs
set	MIN_LIB_NAME	std_ss_ccs
set	DRIVE_CELL		INV2
set	DRIVE_PIN		Y
set	LOAD_CELL		INV4
set	MAX_OP_CON		ff_v1p8_-40c
set	MIN_OP_CON		ss_1p62_125c
set	ALL_IN_EXC_CLK	[remove_from_collection [all_inputs] [get_ports "$CLK_NAME"]]
set	INPUT_DELAY		[expr	$CLK_PERIOD * 0.6]
set_input_delay		$INPUT_DELAY		-clock			$CLK_NAME	$ALL_IN_EXC_CLK
set_driving_cell	-lib_cell	${DIRVE_CELL}	-pin	$DRIVE_PIN 	$ALL_IN_EXC_CLK

## Step 7： Set output delay
set 	OUTPUT_DELAY	[expr	$CLK_PERIOD * 0.6]
set		MAX_LOAD		[expr	[load of	${MAX_LIB_NAME}/$LOAD_CELL/$LOAD_PIN] * 10 ]
set_output_delay		$OUTPUT_DELAY	-clock	$CLK_NAME	[all_outputs]
set_load				[expr	$MAX_LOAD * 3]				[all_outputs]
set_isolate_ports		-type buffer						[all_outputs]

## Step 8: Set max delay for comb logic
set_input_delay		[expr $CLK_PERIOD * 0.1]	-clock	$CLK_NAME	-add_delay	[get_ports	spi_i]
set_output_delay	[expr $CLK_PERIOD * 0.1]	-clock	$CLK_NAME	-add_delay	[get_ports	spi_o]

## Step 9：Set operating condition & wire load model
set_operating_conditions	-max			$MAX_OPERA_CONDITION	\
							-max_library	$MAX_LIB_NAME	\
							-min			$MIN_OPERA_CONDITION	\
							-min_library	$MIN_LIB_NAME	
set	auto_wire_load_selection	false
set_wire_load_mode	top
#set_wire_load_mode	-name	$WIRE_LOAD_MODEL	\
							-library	$MAX_LIB_NAME
## Step 10：Set area constraint (Let DC try its best)
set_max_area 0

## Step 11：Set DRC constraint
set	MAX_CAPACITANCE	[expr	[load of $LIB_NAME/NAND4X2/Y] * 5]
set_max_capacitance	$MAX_CAPACITANCE	$ALL_IN_EXC_CLK

## Step 12: Set DRC constraint
## for debug constraint and design critical path
group_path	-name	$CLK_NAME	-weight 5 \
			-critical_range	[expr $CLK_PERIOD * 0.1]
group_path	-name	INPUT	-from	[all_inputs]	\
			-critical_range	[expr $CLK_PERIOD * 0.1]
group_path	-name	OUTPUTS	-to		[all_outputs]
			-critical_range [expr $CLK_PERIOD * 0.1]
group_path	-name	COMBI	-from	[all_inputs]	\
			-to						[all_outputs]	\
			-critical_range	[expr $CLK_PERIOD * 0.1]
## Step 13: Elimate the multiple_port inter-connect & define name style
set_app_var	verilogout_show_unconnected_pins	true
set_app_var	bus_naming_style	{%s[%d]}
set_fix_multiple_port_nets	-all	-buffer_constants

## Step 14: Timing exception define
#set_false_path	-from	[get_clocks clk1_i]	-to [get_clocks clk2_i]
#set				ALL_CLOCKS	[all_clocks]
#foreach_in_collection CUR_CLK	$ALL_CLOCKS	{
#	set OTHER_CLKS	[remove_from_collection [all_clocks]	$CUR_CLK]
#	set_false_path	-from	$CUR_CLK	-to	$OTHER_CLKS
#}

#set_false_path -from [get_clocks $CLK1_NAME] -to [get_clocks $CLK2_NAME]
#set_disable_timing	TOP/U1	-from	YOUR_DEFINE_A	\
#							-to		YOUR_DEFINE_B
#set_case_analysis			0		[get_ports	sel_i]
#set_multicycle_path	-setup	6	-from	FFA/CP	-through ADD/out -to FFB/D
#set_multicycle_path	-hold 	5	-from	FFA/CP	-through ADD/out -to FFB/D
#set_multicycle_path	-setup	2	-to		[get_pins	YOUR_DEF2/D]
#set_multicycle_path	-hold	1	-to		[get_pins	YOUR_DEF2/D]

## Step 15: Compile	flow
#ungroup	-flatten	-all
####----- 1st-pass compile
#compile	-map_effort high -area_effort high
#compile	-map_effort high -area_effort high -boundary_optimization
compile 	-map_effort high -area_effort high -scan

#simplify_constants	-boundary_optimization
#compile 	-map_effort high -area_effort high -incremental_mapping -scan
####----- 2nd-pass compile
#compile_ultra	-incr

## Step 16: Write post_process files
change_names	-rules	verilog	-hier
#remove_unconnected_ports	[get_cells	-hier	*]	-blast_buses
####----- Write the mapped files
write -f ddc		-hier -output	$OUTPUT_PATH/$TOP_DESIGN.ddc
write -f verilog	-hier -output	$OUTPUT_PATH/$TOP_DESIGN.v
write_sdc			-version 1.7	$OUTPUT_PATH/$TOP_DESIGN.sdc
write_sdf			-version 2.1	$OUTPUT_PATH/$TOP_DESIGN.sdf

## Step 17: Generate report files
## Get report file
redirect	-tee	-file	$REPORT_PATH/check_design.rpt	{check_design}
redirect	-tee	-file	$REPORT_PATH/check_timing.rpt	{check_timing}
redirect	-tee	-file	$REPORT_PATH/rpt_constraint.rpt	{report_constraint -all_violators}
redirect	-tee	-file	$REPORT_PATH/check_setup.rpt	{report_timing -delay_type max}
redirect	-tee	-file	$REPORT_PATH/check_hold.rpt		{report_timing -delay_type min}
redirect	-tee	-file	$REPORT_PATH/rpt_area.rpt		{report_area	}
redirect	-tee	-file	$REPORT_PATH/rpt_path_group.rpt	{report_path_group}
redirect	-tee	-file	$REPORT_PATH/rpt_timing_req.rpt	{report_timing_requirements}

## Step 18: At the end
sh rm command.log
sh rm default.svf
exit