【HDLBITS 】couter clock

HDLBITS couter clock

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
   
    reg [7:0] hhh;
    reg [7:0] mmm;
    reg [7:0] sss;
    reg pmm;
    
    assign hh = hhh;
    assign mm = mmm;
    assign ss = sss;
    assign pm = pmm;
    
    wire [4:0] add;
    wire apt;//am ->pm or pm->am
    
    always@(posedge clk) begin
        if(reset) begin
           hhh <= 8'h12;
            mmm <= 8'd0;
            sss <= 8'd0;
        end
        else if(ena&hhh == 8'h12 & add[1] & add[3]) begin//12:59:59->1:00:00
           	hhh <= 8'h01; 
            mmm[7:0] <= 8'h0;
            sss[7:0] <= 8'h0;
        end
        else if(ena&add[4]&add[3]&add[1]) begin//09:59:59->10:00:00
            hhh[7:4] <= hhh[7:4] + 4'b1;
            hhh[3:0] <= 4'd0;
            mmm[7:0] <= 8'd0;
            sss[7:0] <= 8'd0; 
        end
        else if(ena&add[3]&add[1]) begin//1~8:59:59->2~9:00:00
            hhh[3:0] <= hhh[3:0] + 4'b1;
            mmm[7:0] <= 8'd0;
            sss[7:0] <= 8'd0;
        end
        else if(ena&add[2]&add[1]) begin//00:*9:59->00:(*+1)0:00
            mmm[7:4] <= mmm[7:4] + 4'b1; 
            mmm[3:0] <= 4'd0;
            sss[7:0] <= 8'd0;
        end
        else if(ena&add[1]) begin//00:00:59->00:0*:00
            mmm[3:0] <= mmm[3:0] + 4'b1; 
            sss[7:0] <= 8'd0;
        end
        else if(ena&add[0]) begin//00:00:*9->00:00:(*+1)0
            sss[7:4] <= sss[7:4] + 4'b1;
            sss[3:0] <= 4'd0;
        end
        else if(ena) begin
            sss[3:0] <= sss[3:0] + 4'b1;
        end
        else sss[3:0] <= sss[3:0];
    end
    //pmm 
    always@(posedge clk) begin
        if(reset) pmm <= 1'b0;
        else if(apt&add[1]&add[3]) pmm <= ~pmm;//11:59:59 am -> pm / pm -> am
        else pmm <= pmm;
    end
	//sss
    always@(*) begin
        case(sss)
            8'h09,8'h19,8'h29,8'h39,8'h49: add[0] = 1'b1;// 9->10,19->20,~~~~
            8'h59: add[1] = 1'b1;
           	default:add[1:0] = 2'b0;
        endcase
    end
    //mmm
    always@(*) begin
        case(mmm)
            8'h09,8'h19,8'h29,8'h39,8'h49: add[2] = 1'b1;// 9->10,19->20,~~~~
            8'h59: add[3] = 1'b1;
            default:add[3:2] = 2'b0;
        endcase
    end
    //hhh control
    always@(*) begin
        case(hhh)
            8'h09: add[4] = 1'b1;
            8'h11: apt = 1'b1;
            default:begin
                add[4] = 1'b0;
                apt = 1'b0;
            end
        endcase
    end

endmodule