author | ||
Wed, 3 Jul 2013 05:47:35 +0000 (13:47 +0800) | ||
committer | YuBing <billyu@anydata.com> | |
Thu, 4 Jul 2013 01:22:45 +0000 (09:22 +0800) | ||
commit | 45297924b20673362aa9670879f16ac1c85ed692 | |
tree | 8af404d169cc98ee0e5a317672971a6de9435832 | tree |
parent | 6ae53c38bd7f29c953a6843a9c35554c8027ba4c | commit | diff |
fix lcd bluescreen issue
static struct mipi_dsi_phy_ctrl mipi_dsi_himax_hx8363a_panel_phy_ctrl = {
+#if 1
+
+ /* DSI_BIT_CLK at 400MHz, 2 lane, RGB888 */
+ /* regulator */
+ {0x03, 0x01, 0x01, 0x00},
+ /* timing */
+ {0xaa, 0x3b, 0x1b, 0x00, 0x52, 0x58, 0x20, 0x3f,
+ 0x2e, 0x03, 0x04},
+ /* phy ctrl */
+ {0x7f, 0x00, 0x00, 0x00},
+ /* strength */
+ {0xee, 0x00, 0x86, 0x00},
+ /* pll control */
+ {0x40, 0xc7, 0xb0, 0xda, 0x00, 0x50, 0x48, 0x63,
+ 0x30, 0x07, 0x03,
+ 0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0},
+#else
/* DSI_BIT_CLK at 360MHz, 2 lane, RGB888 */
/* regulator */
{0x03, 0x01, 0x01, 0x00},
{0x40, 0x67, 0x01, 0x1a, 0x00, 0x50, 0x48, 0x63,
0x31, 0x0f, 0x07,
0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0},
-
+#endif
};
#endif // DISPLAY_MIPI_PANEL_HIMAX
gpio_set(MSM_GPIO_MIPI_RESET, 1);
mdelay(1);
gpio_set(MSM_GPIO_MIPI_RESET, 0);
- mdelay(1);
+ mdelay(3);
gpio_set(MSM_GPIO_MIPI_RESET, 1);
- mdelay(120);
+ mdelay(10);
#endif
cm = cmds;
unsigned char DLNx_EN;
// video mode data ctrl
int status = 0;
-#if DISPLAY_MIPI_PANEL_HIMAX
- unsigned long low_pwr_stop_mode = 0;
+#if 0//DISPLAY_MIPI_PANEL_HIMAX
+ unsigned long low_pwr_stop_mode = 1;
unsigned char eof_bllp_pwr = 1;
#else
unsigned long low_pwr_stop_mode = 1;
writel(1, DSI_EOT_PACKET_CTRL);
writel(0x00000100, DSI_MISR_VIDEO_CTRL);
-#if DISPLAY_MIPI_PANEL_HIMAX
+#if 0//DISPLAY_MIPI_PANEL_HIMAX
writel(0 << 28 | 0 << 24 | 0 << 20 | low_pwr_stop_mode << 16 | eof_bllp_pwr << 15 | 0 << 12 | TRAFIC_MODE << 8
| DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
#else
#define MIPI_VSYNC_FRONT_PORCH_LINES 5
#elif DISPLAY_MIPI_PANEL_HIMAX
-
+#if 0
#define MIPI_HSYNC_PULSE_WIDTH 8
#define MIPI_HSYNC_BACK_PORCH_DCLK 10
#define MIPI_HSYNC_FRONT_PORCH_DCLK 8
#define MIPI_VSYNC_PULSE_WIDTH 8
#define MIPI_VSYNC_BACK_PORCH_LINES 10
#define MIPI_VSYNC_FRONT_PORCH_LINES 10
+#else
+#define MIPI_HSYNC_PULSE_WIDTH 5
+#define MIPI_HSYNC_BACK_PORCH_DCLK 400
+#define MIPI_HSYNC_FRONT_PORCH_DCLK 50
+
+#define MIPI_VSYNC_PULSE_WIDTH 1
+#define MIPI_VSYNC_BACK_PORCH_LINES 75
+#define MIPI_VSYNC_FRONT_PORCH_LINES 5
+#endif
#else
#ifdef CONFIG_FB_MSM_LCDC_LG97_XGA
#define MSM_FB_PRIM_BUF_SIZE \
(roundup((1024 * 768 * 4), 4096) * 3) /* 4 bpp x 3 pages */
+#elif defined(CONFIG_ANY_ASP_OT300)
+#define MSM_FB_PRIM_BUF_SIZE \
+ (roundup((800* 480 * 4), 4096) * 3) /* 4 bpp x 3 pages */
#else
#define MSM_FB_PRIM_BUF_SIZE \
(roundup((1024 * 600 * 4), 4096) * 3) /* 4 bpp x 3 pages */
#ifdef CONFIG_FB_MSM_LCDC_LG97_XGA
#define MSM_FB_PRIM_BUF_SIZE \
(roundup((1024 * 768 * 4), 4096) * 2) /* 4 bpp x 2 pages */
+#elif defined(CONFIG_ANY_ASP_OT300)
+#define MSM_FB_PRIM_BUF_SIZE \
+ (roundup((800* 480 * 4), 4096) * 2) /* 4 bpp x 2 pages */
#else
#define MSM_FB_PRIM_BUF_SIZE \
(roundup((1024 * 600 * 4), 4096) * 2) /* 4 bpp x 2 pages */
#define MSM_FB_EXT_BUF_SIZE \
(roundup((720 * 576 * 2), 4096) * 2) /* 2 bpp x 2 pages */
#else
-#define MSM_FB_EXT_BUFT_SIZE 0
+#define MSM_FB_EXT_BUF_SIZE \
+ (roundup((1920 * 1080 * 2), 4096) * 1) /* 2 bpp x 2 page */
#endif
/* Note: must be multiple of 4096 */
#endif
#ifdef CONFIG_FB_MSM_OVERLAY0_WRITEBACK
-#define MSM_FB_OVERLAY0_WRITEBACK_SIZE roundup((1376 * 768 * 3 * 2), 4096)
+#if defined(CONFIG_ANY_ASP_OT300)
+#define MSM_FB_OVERLAY0_WRITEBACK_SIZE roundup((800 * 480 * 3 * 2), 4096)
+#else
+#define MSM_FB_OVERLAY0_WRITEBACK_SIZE roundup((1280 * 720 * 3 * 2), 4096)
+#endif
#else
#define MSM_FB_OVERLAY0_WRITEBACK_SIZE (0)
#endif /* CONFIG_FB_MSM_OVERLAY0_WRITEBACK */
#else
.mem_hid = MEMTYPE_EBI1,
#endif
+#ifdef CONFIG_FB_MSM_MIPI_DSI
+ .cont_splash_enabled = 1,
+#endif
};
static void __init reserve_mdp_memory(void)
static struct mipi_dsi_phy_ctrl dsi_video_mode_phy_db = {
// Need update this struct by qualcomm Here.
-
+#if 1
+ /* DSI_BIT_CLK at 400MHz, 2 lane, RGB888 */
+ /* regulator */
+ {0x03, 0x01, 0x01, 0x00},
+ /* timing */
+ {0xaa, 0x3b, 0x1b, 0x00, 0x52, 0x58, 0x20, 0x3f,
+ 0x2e, 0x03, 0x04},
+ /* phy ctrl */
+ {0x7f, 0x00, 0x00, 0x00},
+ /* strength */
+ {0xee, 0x00, 0x86, 0x00},
+ /* pll control */
+ {0x40, 0xc7, 0xb0, 0xda, 0x00, 0x50, 0x48, 0x63,
+ 0x30, 0x07, 0x03,
+
+ 0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0},
+#else
/* DSI_BIT_CLK at 360MHz, 2 lane, RGB888 */
/* regulator */
{0x03, 0x01, 0x01, 0x00},
0x31, 0x0f, 0x07,
0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0},
-
+#endif
};
pinfo.bpp = 24;
-#if 1
+#if 0
pinfo.lcdc.h_back_porch = 10;
pinfo.lcdc.h_front_porch = 8;
pinfo.lcdc.h_pulse_width = 8;
pinfo.fb_num = 2;
pinfo.mipi.mode = DSI_VIDEO_MODE;
-#if 0
+#if 1
pinfo.mipi.pulse_mode_hsa_he = TRUE;
pinfo.mipi.hfp_power_stop = TRUE;
pinfo.mipi.hbp_power_stop = TRUE;