1 理论学习
2 实战演练
2.1 设计规划
2.2 波形绘制
2.3 代码编写和编译
module key_filter
#(
parameter CNT_MAX = 20'd999_999;
)
(
input wire sys_clk,
input wire sys_rst_n,
input wire key_in,
output key_flag
);
reg [19:0]cnt_20ms;
always@(posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n)
cnt_20ms <= 20'd0;
else if(key_in == 1'd1)
cnt_20ms <= 20'd0;
else if(cnt_20ms == CNT_MAX)
cnt_20ms <= CNT_MAX;
else
cnt_20ms <= cnt_20ms + 1'd1;
end
always@(posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n)
key_flag <= 1'd0;
else if(cnt_20ms == (CNT_MAX - 20'd1))
key_flag <= 1'd1;
else
key_flag <= 1'd0;
end
仿真文件:
`timescale 1ns/1ns
module tb_key_filter();
reg sys_clk;
reg sys_rst_n;
reg key_in;
reg [7:0]tb_cnt;
wire key_flag;
initial begin
sys_clk <= 1'b1;
sys_rst_n <= 1'b0;
#20
sys_rst_n <= 1'b1;
end
always@(posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n)
tb_cnt <= 8'd0;
else if(tb_cnt == 8'd249)
tb_cnt <= 8'd0;
else
tb_cnt <= tb_cnt + 8'd1;
end
always@(posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n)
key_in <= 1'd1;
....
end
endmodule
没时间写了: