FPGA学习之大道至简计数器模板

1 计数器模板

wire add_cnt0;
wire end_cnt0;

reg [28:0] cnt0;
localparam TIME_10MS = 40_000;

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 			cnt0 <= 0;
	else if(add_cnt0) begin
		if(end_cnt0)	cnt0 <= 0;
		else			cnt0 <= cnt0 + 1;
	end
end

assign add_cnt0 = 1;
assign end_cnt0 = add_cnt0 && cnt0 == TIME_10MS - 1;