vhdl数字逻辑

8D锁存器的功能

LIBRARY IEEE;

USEIEEE.SRD_LOGIC_1164.ALL;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CT74273 IS

    PORT(D1,D2,D3,D4,D5,D6,D7,D8,CRN,CP:INSTD_LOGIC;

Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8:OUT STD_LOGIC);

END CT74273;

ARCHITECTURE one OFCT74273 IS

    SIGNAL D_SIGNAL:STD_LOGIC_VECTOR(8 DOWNTO1);

    SIGNAL Q_SIGNAL:STD_LOGIC_VECTOR(8 DOWNTO1);

BEGIN

PROCESS(D1,D2,D3,D4,D5,D6,D7,D8,CRN,CP)

BEGIN

    D_SIGNAL <=(D8&D7&D6&D5&D4&D3&D2&D1);

    IF CRN = ‘0’THEN Q_SIGNAL <=”00000000”;

    ELSE CP’EVENT AND CP’ = ‘1’THEN

        Q_SIGNAL <= D_SIGNAL;

END IF;

Q1 <=Q_SIGNAL(1);

Q1 <=Q_SIGNAL(2);

Q1 <=Q_SIGNAL(3);

Q1 <=Q_SIGNAL(4);

Q1 <=Q_SIGNAL(5);

Q1 <=Q_SIGNAL(6);

Q1 <=Q_SIGNAL(7);

Q1 <=Q_SIGNAL(8);

END PROCESS;

END one;