四位数值比较器

LIBRARY IEEE;  
USE IEEE.std_logic_1164.all; 
entity com_4 is  
    port(a,b:in std_logic_vector(3 downto 0);     
end entity;  
architecture struct of com_4 is  
    component com_1 is   
        port(a,b:in std_logic;       
            q:out std_logic_vector(2 downto 0));  
    end component;  
    signal q0,q1,q2,q3:std_logic_vector(2 downto 0);
    begin   
        u0:com_1 port map(a(0),b(0),q0);   
        u1:com_1 port map(a(1),b(1),q1);   
        u2:com_1 port map(a(2),b(2),q2);   
        u3:com_1 port map(a(3),b(3),q3);     
    process(q0,q1,q2,q3)is   
    begin   
        if(q3/="010") then  
            q<=q3;    
        elsif(q2/="010") then   
            q<=q2;    
        elsif(q1/="010") then   
            q<=q1;    
        elsif(q0/="010") then   
            q<=q0;    
        else    
            q<="010";    
        end if;  
    end process; 
end architecture;