FPGA verilog 简单的平方根求法

用下面的平方根求法不需要乘法，只需简单的移位就能实现。

function [15:0] sqrt;
      input [31:0] num;  //declare input
      //intermediate signals.
      reg [31:0] a;
      reg [15:0] q;
      reg [17:0] left,right,r;    
      integer i;
  begin
      //initialize all the variables.
      a = num;
      q = 0;
      i = 0;
      left = 0;   //input to adder/sub
      right = 0;  //input to adder/sub
      r = 0;  //remainder
      //run the calculations for 16 iterations.
      for(i=0;i<16;i=i+1) begin 
          right = {q,r[17],1'b1};
          left = {r[15:0],a[31:30]};
          a = {a[29:0],2'b00};    //left shift by 2 bits.
          if (r[17] == 1) //add if r is negative
              r = left + right;
          else    //subtract if r is positive
              r = left - right;
          q = {q[14:0],!r[17]};       
      end
      sqrt = q;   //final assignment of output.
  end
  endfunction 

原理参照论文A New Non-Restoring Square Root Algorithm and Its VLSI Implementations