基于BT1120协议生成SDI(HDMI)彩条

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已于 2024-01-25 12:48:34 修改

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文章标签： fpga开发

于 2023-07-20 11:19:00 首次发布

本文链接：https://blog.csdn.net/qq_35318223/article/details/131826174

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该代码描述了一个基于Verilog的FPGA状态机设计，用于控制VBANK和ACTVIDEO两个阶段的结束条件。当行计数和列计数满足特定条件时，状态会从VBANK转移到ACTVIDEO，反之亦然。设计中包含了时钟边沿检测、复位处理以及状态转换逻辑。

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always @(posedge clk_148p5MHz or posedge rst) begin
	if (rst) begin
		vbank_end<=1'b0;		
	end
	else if (row_cnt=='d41   && col_cnt==TOTAL_COL) begin
		vbank_end<=1'b1;	
	end
	else begin
		vbank_end<=1'b0;
	end
end

always @(posedge clk_148p5MHz or posedge rst) begin
	if (rst) begin
		actvideo_end<=1'b0;		
	end
	else if (row_cnt=='d1121 && col_cnt==TOTAL_COL) begin
		actvideo_end<=1'b1;	
	end
	else begin
		actvideo_end<=1'b0;	
	end
end

always @(posedge clk_148p5MHz or posedge rst) begin
	if (rst) begin
		current_state<=VBANK;
	end
	else  begin
		current_state<=next_state;
	end
end

always @(*) begin
	case (current_state)
		VBANK:begin
			if(vbank_end==1'b1)begin
				next_state=ACTVIDEO;
			end
			else begin
				next_state=VBANK;
			end
		end
		ACTVIDEO:begin
			if (actvideo_end==1'b1)begin
				next_state=VBANK;
			end
			else begin
				next_state=ACTVIDEO;
			end
		end
	endcase 
end