VHDL 有限状态机(FSM) 代码示例

示例一 "10"检测器

library ieee;
use ieee.std_logic_1164.all;
entity FSM is
	port(Din,CLK,Reset:in std_logic;Dout:out std_logic);
end FSM;
architecture behave of FSM is
	type state is(S0,S1,S2);
	signal currentstate: state:=S0;
	signal nextstate:state:=S0;
begin
	state_trans:process(Din,currentstate)
	begin
		case currentstate is
			when S0=>if Din='1' then nextstate<=S1;else nextstate<=S0;end if;
			when S1=>if Din='0' then nextstate<=S2;else nextstate<=S1;end if;
			when S2=>if Din='0' then nextstate<=S0;else nextstate<=S1;end if;
		end case;
	end process;
	state_latch:process(CLK,reset)
	begin
		if reset='0' then
			currentstate<=S0;
		else
			if CLK'event and CLk='1' then
				currentstate<=nextstate;
			end if;
		end if;
	end process;
	Dout<='1' when currentstate=S2 else '0';
end behave;

示例二 十进制计数器

library ieee;
use ieee.std_logic_1164.all;
entity FSM is
	port(CLK,Reset,enable:in std_logic;Y:out std_logic_vector(3 downto 0);carry:out std_logic);
end FSM;
architecture behave of FSM is
	type state is(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
	signal currentstate:state:=S0;
	signal nextstate:state:=S0;
begin
	process(currentstate)
	begin
		case currentstate is
			when S0=>if enable='1' then nextstate<=S1;else nextstate<=S0;end if;
			when S1=>if enable='1' then nextstate<=S2;else nextstate<=S1;end if;
			when S2=>if enable='1' then nextstate<=S3;else nextstate<=S2;end if;
			when S3=>if enable='1' then nextstate<=S4;else nextstate<=S3;end if;
			when S4=>if enable='1' then nextstate<=S5;else nextstate<=S4;end if;
			when S5=>if enable='1' then nextstate<=S6;else nextstate<=S5;end if;
			when S6=>if enable='1' then nextstate<=S7;else nextstate<=S6;end if;
			when S7=>if enable='1' then nextstate<=S8;else nextstate<=S7;end if;
			when S8=>if enable='1' then nextstate<=S9;else nextstate<=S8;end if;
			when S9=>if enable='1' then nextstate<=S0;else nextstate<=S9;end if;
		end case;
	end process;
	process(clk,reset)
	begin
		if reset='0' then
			currentstate<=S0;
		elsif CLK'event and CLK='1' then
			if enable='1' then
				Currentstate<=nextstate;
			end if;
		end if;
	end process;
	with currentstate select
		Y<="0000" when S0,
			"0001" when S1,
			"0010" when S2,
			"0011" when S3,
			"0100" when S4,
			"0101" when S5,
			"0110" when S6,
			"0111" when S7,
			"1000" when S8,
			"1001" when S9;
	carry<='1' when currentstate=S9 else '0';
end behave;

By-Round Moon