重温FPGA设计流程(四、有限状态机)

软件：Vivado2017.4 板卡：Ego1 型号：xc7a35tcsg324-1
四、有限状态机

Moore状态机

只与当前状态有关而与输入无关

`timescale 1ns / 1ps
module seqdetea(
    input wire clk,
    input wire clr,
    input wire din,
    output reg dout
    );
    reg[2:0]present_state,next_state;
    parameter S0=3'b000,S1=3'b001,S2=3'b010,S3=3'b011,S4=3'b100;
    //状态寄存器
    always@(posedge clk or posedge clr)
        begin
            if(clr == 1)
                present_state <=S0;
            else
                present_state <=next_state;
        end
    //C1模块
    always@(*)
        begin
            case(present_state)
                S0:if(din == 1)
                        next_state <= S1;
                   else
                        next_state <= S0;
                S1:if(din == 1)
                        next_state <= S2;