设计实例04-异步fifo设计

设计代码部分

代码如下：

module async_fifo
#(
  parameter WIDTH = 8,
  parameter DEPTH = 8
)
( 
  input wr_clk,
  input wr_rstn,
  input wr_en,
  input [WIDTH-1:0] wr_data,
  
  input rd_clk,
  input rd_rstn,
  input rd_en,
  output reg [WIDTH-1:0] rd_data,

  output reg full,
  output reg empty
);

  /*read and write ptr*/
  reg [$clog2(DEPTH):0] wr_ptr, rd_ptr;

  /*fifo ram*/
  reg [WIDTH-1:0] fifo_ram[DEPTH-1:0];

  /*write data to ram_fifo*/
  integer i;
  always @(posedge wr_clk or negedge wr_rstn) begin
    if(!wr_rstn)
      for(i=0;i<DEPTH;i=i+1)
        fifo_ram[i] <= {
   WIDTH{
   1'b0}};
    else if(wr_en && (!full))
      fifo_ram[wr_ptr] <= wr_data;
  end
  
  /*write ptr logic*/
  always @(posedge wr_clk or negedge wr_rstn) begin
    if(!wr_rstn)
      wr_ptr <= 0;
    else if(wr_en && (<