问题:下级模块入口fifo
的阈值是3
,如何在上级模块计算rdy
,限制上级模块的发包速度?
module top(
input clk,
input rst_n,
input cack,
input push,
output rdy
);
reg[7:0] credit_thr = 8'h3;
reg[7:0] cnt, cnt_next;
always @(*) begin
cnt_next = cnt;
case({cack, push})
2'b01: cnt_next = cnt + 1;
2'b10: cnt_next = cnt - 1;
endcase
end
always @(posedge clk, negedge rst_n) begin
if(~rst_n) begin
cnt <= 8'b0;
cnt_next <= 8'b0;
rdy <= 1'b0;
end
else begin
cnt <= cnt_next;
rdy <= (cnt_next < credit_thr);
end
end
endmodule
另外合并写法:
module top(
input clk,
input rst_n,
input cack,
input push,
output rdy
);
reg[7:0] credit_thr = 8'h3;
reg[7:0] cnt;
always @(posedge clk, negedge rst_n) begin
if(~rst_n) begin
cnt <= 8'b0;
rdy <= 1'b0;
end
else begin
case(cack, push)
2'b00,
2'b11: begin
rdy <= (cnt < credit_thr);
end
2'b01: begin
cnt <= cnt + 1; //下一拍赋值
rdy <= ((cnt + 1) < credit_thr); //注意是在当拍计算rdy信号,cnt要加1
end
2'b10: begin
cnt <= cnt - 1;
rdy <= ((cnt - 1) < credit_thr);
end
endcase
end
end
endmodule